Справочник Пользователя для Novatel Wireless NRM-EU870D
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Novatel Wireless
Revision 1
SM Bus Design Guidelines
Introduction
This section will describe the SMBus interface parameters ensuring interoperability with Novatel’s
PCI Express Mini Cards the SM Bus interface.
The SMBus is a two-wire interface through which various system components can communicate
with each other and the rest of the system. It is based on the principles of operation of I
This section will describe the SMBus interface parameters ensuring interoperability with Novatel’s
PCI Express Mini Cards the SM Bus interface.
The SMBus is a two-wire interface through which various system components can communicate
with each other and the rest of the system. It is based on the principles of operation of I
2
C. See
the PCI Express Card Electromechanical Specification for more details on the functional
requirements for the SMBus.
The SMB_CLK signal and the SMB_DAT signal are available on pins 30 and 32 of the PCI
Express Mini connector.
requirements for the SMBus.
The SMB_CLK signal and the SMB_DAT signal are available on pins 30 and 32 of the PCI
Express Mini connector.
This interface will support a subset of the specification as detailed in this section.
SMBus is an i2c based protocol that will drive a slave device and report various data regarding
mobile status or real-time e-mail to it, in accordance to the SMBus protocol specification. It is
important to note that the EU860D/EU870D & E725 PCI Express Mini-card acts as a bus
master and not as a slave.
I2C Controller
The controller is an I2C-compliant, master-only device. The controller can access all available I2C
slaves on the bus, but cannot be accessed by any other masters on the bus.
Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a current-
source or pull-up resistor. When the bus is free, both lines are HIGH. The output stages of
devices connected to the bus must have an open-drain or open-collector to perform the wired-
AND function.
A simplified version of the I2C bus operation is as follows:
The controller is an I2C-compliant, master-only device. The controller can access all available I2C
slaves on the bus, but cannot be accessed by any other masters on the bus.
Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a current-
source or pull-up resistor. When the bus is free, both lines are HIGH. The output stages of
devices connected to the bus must have an open-drain or open-collector to perform the wired-
AND function.
A simplified version of the I2C bus operation is as follows:
• The master generates a START condition, signaling all ICs on the bus to listen for data.
• The master writes a 7-bit address, followed by a read/write bit to select the device as a
transmitter or receiver.
• The receiver sends an acknowledge bit over the bus. The transmitter must read this bit to
determine whether or not the addressed device is on the bus.
• Depending on the value of the read/write bit, any number of 8-bit messages can be
transmitted or received by the master. These messages are specific to the I2C device
used. After 8 message bits are written to the bus, the transmitter will receive an
acknowledge bit. This message and acknowledge transfer continues until the entire
message is transmitted.
used. After 8 message bits are written to the bus, the transmitter will receive an
acknowledge bit. This message and acknowledge transfer continues until the entire
message is transmitted.
• The message is terminated by the master with a STOP condition. This frees the bus for
the next master to begin communications.
• Data on the I2C-bus can be transferred at rates of up to 100 kbps in the Standard-mode,
• The number of interfaces connected to the bus is solely dependent on the bus
capacitance limit of 400 pF.