Справочник Пользователя для Selex Sistemi Integrati Inc. VOR2
Model 1150A DVOR
2-20
Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
Figure 2-9 Carrier Amplifier Assembly Block Diagram
2.3.2.4.2 Power Amplifier Assembly Detailed Circuit Theory
Refer to
Figure 11-19
An input CW RF signal is generated from the VOR synthesizer module with a minimum
output power level of 100mW. The RF is sent through a cable to the carrier amplifier assembly. Once the RF enters
the amplifier, it is attenuated through a 3 dB attenuator before entering the driver stage of the amplifier. The 3 dB
attenuator serves to provide a resistive load for the synthesizer module. The RF is modulated with the Q6 driver
stage. The driver is an LDMOS type RF FET with high gain and good linearity. Q6 is modulated using a gate
modulation technique. The gate of Q6 is voltage-varied, which modulates the RF signal. This is accomplished by
using a feedback circuit that samples the output of the amplifier using C80, C81, and R42. The feedback signal is
attenuated through R69, R70, and R71. This signal is routed to the detector, U21 where the audio is detected and
buffered through U22:D. The input to the detector circuit is a 14 dB attenuator, R69, R70, and R71 followed by a
coupling capacitor C116 into U21. U21 is a high linearity, true power, single chip detector.
the amplifier, it is attenuated through a 3 dB attenuator before entering the driver stage of the amplifier. The 3 dB
attenuator serves to provide a resistive load for the synthesizer module. The RF is modulated with the Q6 driver
stage. The driver is an LDMOS type RF FET with high gain and good linearity. Q6 is modulated using a gate
modulation technique. The gate of Q6 is voltage-varied, which modulates the RF signal. This is accomplished by
using a feedback circuit that samples the output of the amplifier using C80, C81, and R42. The feedback signal is
attenuated through R69, R70, and R71. This signal is routed to the detector, U21 where the audio is detected and
buffered through U22:D. The input to the detector circuit is a 14 dB attenuator, R69, R70, and R71 followed by a
coupling capacitor C116 into U21. U21 is a high linearity, true power, single chip detector.
U12:A is an error
amplifier used to compare the input reference signal to correct for non-linearity in the RF amplifier. From the driver
stage, the RF signal is attenuated using AT1 to help balance any slight impedance differences between the driver and
final RF stages. Attenuator AT1 also helps with a wider bandwidth. The signal is then routed to the final amplifier
stage, Q7. The Q7 amplifier is another LDMOS type RF FET with high gain and good linearity. The Q6 amplifier
is biased at approximately 850mA. The biasing of the stage is set with potentiometer R36, U13, R35, and CR5 to
adjust the quiescent (no RF applied) current level to produce a voltage drop of 17mV across test points TP7 and
TP8. Diode CR5 provides thermal compensation for Q6. The minimum gain from the final amp stage is +20 dB.
stage, the RF signal is attenuated using AT1 to help balance any slight impedance differences between the driver and
final RF stages. Attenuator AT1 also helps with a wider bandwidth. The signal is then routed to the final amplifier
stage, Q7. The Q7 amplifier is another LDMOS type RF FET with high gain and good linearity. The Q6 amplifier
is biased at approximately 850mA. The biasing of the stage is set with potentiometer R36, U13, R35, and CR5 to
adjust the quiescent (no RF applied) current level to produce a voltage drop of 17mV across test points TP7 and
TP8. Diode CR5 provides thermal compensation for Q6. The minimum gain from the final amp stage is +20 dB.
A small RF sample is coupled from the output of the final amplifier stage through C67. The sample is low pass
filtered and sent to the front panel of the module for a test equipment test point. The front panel sample is intended
to replicate the high power output filter of the amplifier.
The RF output of the final amplifier stage is then capacitive coupled through C66 to the output filter. The output
filter C69, L24, C71, L26, C72, C74, L28, C76, C78, and L29 is a low pass filter designed to remove harmonics
from the carrier RF signal.
A small RF sample is coupled from the output of the low pass filter through C84. The small sample is the carrier
feedback to the RF synthesizer via J3.
filtered and sent to the front panel of the module for a test equipment test point. The front panel sample is intended
to replicate the high power output filter of the amplifier.
The RF output of the final amplifier stage is then capacitive coupled through C66 to the output filter. The output
filter C69, L24, C71, L26, C72, C74, L28, C76, C78, and L29 is a low pass filter designed to remove harmonics
from the carrier RF signal.
A small RF sample is coupled from the output of the low pass filter through C84. The small sample is the carrier
feedback to the RF synthesizer via J3.
Another RF sample is coupled from the output of the low pass filter through C80. The sample is sent to the detector
circuit for detection of forward transmitted power.
circuit for detection of forward transmitted power.