Справочник Пользователя для Selex Sistemi Integrati Inc. VOR2
Model 1150A DVOR
Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
2-43
Figure 2-16 LCU Simplified Block Diagram
2.3.2.14.1.1 DC to DC Converter
The LCU receives +48V from the two independent system power supplies and diode OR’s the two sources to
provide input power to a DC to DC converter which supplies all required voltages for the LCU.
2.3.2.14.1.2 Power Fail Detectors
Each of the two independent +48V sources is monitored by a voltage comparator to monitor the health and
availability of power from each of the sources. These signals are used to determine voting logic for the alarm
registers and are reported back to the RMS via the parallel interface.
2.3.2.14.1.3 Key Switch Registers
Front panel switches are de-bounced and held in the Key Switch Registers pending processing by the LCU transfer
state machines. Commands received from the RMS via the parallel interface also control the contents of the Key
Switch Registers. The registers will hold the last command received until the LCU transfer state machine processes
the command.
2.3.2.14.1.4 Parallel Interface
The interface to the RMS is via a parallel data bus consisting of eight (8) data bits, an Address Command line, a
Write Command line, and a Read Command line. The sequence to access internal registers within the LCU consist
of the address being placed on the data bus followed by the strobing of the Address Command line to latch the
address into the internal address register. This is followed by the Read Command line driven true to facilitate a read
from the latched address. For a write command, the address is followed by the data to be written to the LCU
followed by strobing the Write Command line. Alarm Configuration, Bypass Commands, Key Commands, and
basic LCU configuration are some of the bits controlled by the RMS via the parallel interface. State machine Status,
Power-fail Status, System Configuration bits (SCON), and Local/Remote status are some of the status bits that are
readable by the RMS via the parallel interface.
The LCU receives +48V from the two independent system power supplies and diode OR’s the two sources to
provide input power to a DC to DC converter which supplies all required voltages for the LCU.
2.3.2.14.1.2 Power Fail Detectors
Each of the two independent +48V sources is monitored by a voltage comparator to monitor the health and
availability of power from each of the sources. These signals are used to determine voting logic for the alarm
registers and are reported back to the RMS via the parallel interface.
2.3.2.14.1.3 Key Switch Registers
Front panel switches are de-bounced and held in the Key Switch Registers pending processing by the LCU transfer
state machines. Commands received from the RMS via the parallel interface also control the contents of the Key
Switch Registers. The registers will hold the last command received until the LCU transfer state machine processes
the command.
2.3.2.14.1.4 Parallel Interface
The interface to the RMS is via a parallel data bus consisting of eight (8) data bits, an Address Command line, a
Write Command line, and a Read Command line. The sequence to access internal registers within the LCU consist
of the address being placed on the data bus followed by the strobing of the Address Command line to latch the
address into the internal address register. This is followed by the Read Command line driven true to facilitate a read
from the latched address. For a write command, the address is followed by the data to be written to the LCU
followed by strobing the Write Command line. Alarm Configuration, Bypass Commands, Key Commands, and
basic LCU configuration are some of the bits controlled by the RMS via the parallel interface. State machine Status,
Power-fail Status, System Configuration bits (SCON), and Local/Remote status are some of the status bits that are
readable by the RMS via the parallel interface.