Справочник Пользователя для Transcend 128MB SDRAM PC133 Unbuffer Non-ECC Memory TS16MLS64V6G
Модели
TS16MLS64V6G
TS16MLS64V6G
168PIN PC133 Unbuffered DIMM
128MB with 16Mx16 CL3
Transcend information Inc
1
Description
The TS16MLS64V6G is a 16M bit x 64 Synchronous
Dynamic RAM high-density memory module. The
TS16MLS64V6G consists of 4 piece of CMOS 16Mx16bits
Synchronous DRAMs in TFBGA 400mil packages and a
2048 bits serial EEPROM on a 168-pin printed circuit board.
The TS16MLS64V6G is a Dual In-Line Memory Module and
is intended for mounting into 168-pin edge connector
sockets.
Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operation frequencies, programmable
latencies allow the same device to be useful for a variety of
high bandwidth, high performance memory system
applications.
Dynamic RAM high-density memory module. The
TS16MLS64V6G consists of 4 piece of CMOS 16Mx16bits
Synchronous DRAMs in TFBGA 400mil packages and a
2048 bits serial EEPROM on a 168-pin printed circuit board.
The TS16MLS64V6G is a Dual In-Line Memory Module and
is intended for mounting into 168-pin edge connector
sockets.
Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operation frequencies, programmable
latencies allow the same device to be useful for a variety of
high bandwidth, high performance memory system
applications.
Features
• RoHS compliant products.
• Performance Range: PC133.
• Burst Mode Operation.
• Auto and Self Refresh.
• Serial Presence Detect (SPD) with serial
• Performance Range: PC133.
• Burst Mode Operation.
• Auto and Self Refresh.
• Serial Presence Detect (SPD) with serial
EEPROM
• LVTTL compatible inputs and outputs.
• Single 3.3V + 0.3V power supply.
• MRS cycle with address key programs.
• Single 3.3V + 0.3V power supply.
• MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Scramble (Sequential & Interleave)
Burst Length (1,2,4,8 & Full Page)
Data Scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge
of the system clock.
Placement
E
A
B
C
D
G
H
E
I
F
PCB:09-2410