Техническая Спецификация для Intel P4500 CP80617004803AA

Модели

CP80617004803AA

Power Management

Datasheet

The processor exits a package C-state when a break event is detected. Depending on
the type of break event, the processor does the following:

If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.

If the break event is not masked, the target core enters the core C0 state and

the processor enters package C0.

If the break event is masked, the processor attempts to re-enter its previous

package state.

If the break event was due to a memory access or snoop request.

But the platform did not request to keep the processor in a higher package C-

state, the package returns to its previous C-state.

And the platform requests a higher power C-state, the memory access or snoop

request is serviced and the package remains in the higher power C-state.

Table 4-15

shows package C-state resolution for a dual-core processor.

Figure 4-11

summarizes package C-state transitions.

NOTE:
1.

If enabled, the package C-state will be C1E if all actives cores have resolved a core C1
state or higher.

Table 4-15.Coordination of Core Power States at the Package Level

Package C-State

Core 1

Deep Power

Down

Technology

(code named

C6 state)