Справочник Пользователя для Intel III Xeon 500 MHz 80525KX500512
Модели
80525KX500512
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
94
Datasheet
PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width specification in
subsequent rising edge of PWRGOOD. It must also meet the minimum pulse width specification in
The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits
against voltage sequencing issues. The PWRGOOD signal does not need to be synchronized for
FRC operation. It should be driven high throughout boundary scan operation.
against voltage sequencing issues. The PWRGOOD signal does not need to be synchronized for
FRC operation. It should be driven high throughout boundary scan operation.
9.1.40
REQ[4:0]# (I/O)
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all Pentium
III
Xeon processor system bus agents. They are asserted by the current bus owner over two clock
cycles to define the currently active transaction type.
cycles to define the currently active transaction type.
9.1.41
RESET# (I)
Asserting the RESET# signal resets all processors to known states and invalidates their L1 and L2
caches without writing back any of their contents. RESET# must remain active for one
microsecond for a “warm” reset; for a power-on reset, RESET# must stay active for at least one
millisecond after
caches without writing back any of their contents. RESET# must remain active for one
microsecond for a “warm” reset; for a power-on reset, RESET# must stay active for at least one
millisecond after
CCCORE
and CLK have reached their proper specifications. On observing active
RESET#, all Pentium
III
Xeon processor system bus agents will deassert their outputs within two
clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on
configuration. These configuration options are described in the Pentium
configuration. These configuration options are described in the Pentium
®
II Processor Developer’s
Manual.
The processor may have its outputs tri-stated via power-on configuration. Otherwise, if INIT# is
sampled active during the active-to-inactive transition of RESET#, the processor will execute its
Built-In Self-Test (BIST). Whether or not BIST is executed, the processor will begin program
execution at the reset-vector (default 0_FFFF_FFF0h). RESET# must connect the appropriate pins
of all Pentium
sampled active during the active-to-inactive transition of RESET#, the processor will execute its
Built-In Self-Test (BIST). Whether or not BIST is executed, the processor will begin program
execution at the reset-vector (default 0_FFFF_FFF0h). RESET# must connect the appropriate pins
of all Pentium
III
Xeon processor system bus agents.
Figure 44. PWRGOOD Relationship at Power-On
BCLK
WRGOOD
RESET#
Clock Ratio
1 ms
V
CC
L2
V
CORE
CC