Справочник Пользователя для Intel III Xeon 700 MHz 80526KY7002M
Модели
80526KY7002M
ELECTRICAL SPECIFICATIONS
12
Table 1 System Bus-to-Core Frequency Ratio Configuration
1
Ratio of BCLK to
Core Frequency
100 MHz
Target
Frequency
EBL PWRUP
Reg[27,
25:22]
25:22]
LINT[1] LINT[0]
IGNNE#
A20M#
1/4
(Safe-LLLL)
0
0011 L L L L
1/7 700
MHz
0
1001
H
L
H
L
2/18
2
900
MHz
1
0000 X X X X
1/4(Safe-HHHH)
0
1100 H H H H
NOTES:
1.
The frequency multipliers supported are shown in Table 1; other combinations will not be validated nor supported by Intel. Also, each
multiplier is only valid for use on the product of the frequency indicated in Table 1.
multiplier is only valid for use on the product of the frequency indicated in Table 1.
2.
The Pentium® III Xeon™ processor at 900 MHz with 2MB of L2 cache will ignore the logic states presented to the core/bus ratio pins
(A20M#, IGNNE#, LINT0, and LINT1) at the de-assertion of the RESET# signal, and will operate only with a 9:1 core/bus ratio.
(A20M#, IGNNE#, LINT0, and LINT1) at the de-assertion of the RESET# signal, and will operate only with a 9:1 core/bus ratio.
Clock multiplying within the processor is provided by the internal PLL, requiring a constant frequency BCLK input. The
BCLK frequency ratio cannot be changed dynamically during normal operation or any low power modes. The BCLK
frequency ratio for the Pentium® III Xeon™ processor at 700 MHz can be changed when RESET# is active, assuming
that all RESET# specifications are met.
See Figure 1 for the timing relationship between the system bus multiplier signals, RESET#, and normal processor
operation. Using CRESET# (CMOS Reset) and the timing shown in Figure 1, the circuit in Figure 2 can be used to share
these configuration signals. The component used as the multiplexer must not have outputs that drive higher than 2.5V in
order to meet the processor’s 2.5V tolerant buffer specifications.
As shown in Figure 2, the pull-up resistors between the multiplexer and the processor (1K
Ω) force a “safe” ratio into the
processor in the event that the processor powers up before the multiplexer and/or core logic. This prevents the processor
from ever seeing a ratio higher than the final ratio.
If the multiplexer were powered by VCC2.5, a pull-down resistor could be used on CRESET# instead of the four pull-up
resistors between the multiplexer and the processor. In this case, the multiplexer must be designed such that the
compatibility inputs are truly ignored, as their state is unknown.
In any case, the compatibility inputs to the multiplexer must meet the input specifications of the multiplexer. This may
require a level translation before the multiplexer inputs unless the inputs and the signals driving them are already
compatible.
from ever seeing a ratio higher than the final ratio.
If the multiplexer were powered by VCC2.5, a pull-down resistor could be used on CRESET# instead of the four pull-up
resistors between the multiplexer and the processor. In this case, the multiplexer must be designed such that the
compatibility inputs are truly ignored, as their state is unknown.
In any case, the compatibility inputs to the multiplexer must meet the input specifications of the multiplexer. This may
require a level translation before the multiplexer inputs unless the inputs and the signals driving them are already
compatible.
BCLK
RESET#
CRESET#
Ratio Pins#
Compatibility
≤Final Ratio
Final Ratio
000917
Figure 1. Timing Diagram of Clock Ratio Signals