Техническая Спецификация для Intel III 450 MHz 80525PY450512
Модели
80525PY450512
18
Datasheet
Electrical Specifications
2.4.1
Processor V
CC
CORE
Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)
and keep an interconnect resistance from the regulator (or VRM pins) to the SC242 connector of
less than 0.3 m
and keep an interconnect resistance from the regulator (or VRM pins) to the SC242 connector of
less than 0.3 m
Ω
. This can be accomplished by keeping a maximum distance of 1.0 inches between
the regulator output and SC242 connector. The recommended V
CCCORE
interconnect is a 2.0 inch
wide by 1.0 inch long (maximum distance between the SC242 connector and the VRM connector)
plane segment with a 1-ounce plating. Bulk decoupling for the large current swings when the part
is powering on, or entering/exiting low power states, is provided on the voltage regulation module
(VRM). If using Intel’s enabled VRM solutions see developer.intel.com for the specification and a
list of qualified vendors. The V
plane segment with a 1-ounce plating. Bulk decoupling for the large current swings when the part
is powering on, or entering/exiting low power states, is provided on the voltage regulation module
(VRM). If using Intel’s enabled VRM solutions see developer.intel.com for the specification and a
list of qualified vendors. The V
CCCORE
input should be capable of delivering a recommended
minimum dIcc
CORE
) while maintaining the required tolerances (also defined
2.4.2
Processor System Bus AGTL+ Decoupling
The Pentium III processor contains high frequency decoupling capacitance on the processor
substrate; bulk decoupling must be provided for by the system baseboard for proper AGTL+ bus
operation. See AP-906, 100 MHz AGTL+ Layout Guidelines for the Intel
substrate; bulk decoupling must be provided for by the system baseboard for proper AGTL+ bus
operation. See AP-906, 100 MHz AGTL+ Layout Guidelines for the Intel
®
Pentium
®
III Processor
and Intel
®
440BX AGPset (Document Number 245086) or the appropriate platform design guide,
AP-907, Pentium
®
III Processor Power Distribution Guidelines (Document Number 245085), and
the GTL+ buffer specification in the Pentium
®
II Processor Developer's Manual (Document
Number 243502) for more information.
2.5
Processor System Bus Clock and Processor Clocking
The BCLK input directly controls the operating speed of the Pentium III processor system bus
interface. All Pentium III processor system bus timing parameters are specified with respect to the
rising edge of the BCLK input. See the P6 Family of Processors Hardware Developer's Manual
(Document Number 244001) for further details.
interface. All Pentium III processor system bus timing parameters are specified with respect to the
rising edge of the BCLK input. See the P6 Family of Processors Hardware Developer's Manual
(Document Number 244001) for further details.
2.6
Voltage Identification
There are five voltage identification pins on the SC242 connector. These pins can be used to
support automatic selection of power supply voltages. These pins are not signals, but are either an
open circuit or a short circuit to V
support automatic selection of power supply voltages. These pins are not signals, but are either an
open circuit or a short circuit to V
SS
on the processor. The combination of opens and shorts defines
the voltage required by the processor core. The VID pins are needed to cleanly support voltage
specification variations on current and future Pentium III processors. VID[4:0] are defined in
specification variations on current and future Pentium III processors. VID[4:0] are defined in
. A ‘1’ in this table refers to an open pin and a ‘0’ refers to a short to ground. The power
supply must supply the voltage that is requested or disable itself.
To ensure a system is ready for current and future Pentium III processors, the range of values in
bold in
bold in
should be supported. A smaller range will risk the ability of the system to migrate
to a higher performance Pentium III processor and/or maintain compatibility with current
Pentium III processors.
Pentium III processors.