Справочник Пользователя для Intel i7-3920XM Extreme AW8063801009607
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AW8063801009607
Processor Configuration Registers
208
Datasheet, Volume 2
2.11.6
VC0RSTS—VC0 Resource Status Register
This register reports the Virtual Channel specific status.
2.11.7
RCLDECH—Root Complex Link Declaration Enhanced
This capability declares links from this element (PEG) to other elements of the root
complex component to which it belongs. See PCI Express* specification for
link/topology declaration requirements.
complex component to which it belongs. See PCI Express* specification for
link/topology declaration requirements.
B/D/F/Type:
0/6/0/MMR
Address Offset:
11A–11Bh
Reset Value:
0002h
Access:
RO-V
Size:
16 bits
BIOS Optimal Default
0000h
Bit
Access
Reset
Value
RST/
PWR
Description
15:2
RO
0h
Reserved (RSVD)
1
RO-V
1b
Uncore
VC0 Negotiation Pending (VC0NP)
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
(initialization or disabling).
This bit indicates the status of the process of Flow Control
initialization. It is set by default on Reset, as well as whenever
the corresponding Virtual Channel is Disabled or the Link is in the
DL_Down state. It is cleared when the link successfully exits the
FC_INIT2 state.
Before using a Virtual Channel, software must check whether the
Before using a Virtual Channel, software must check whether the
VC Negotiation Pending fields for that Virtual Channel are cleared
in both Components on a Link.
0
RO
0h
Reserved (RSVD)
B/D/F/Type:
0/6/0/MMR
Address Offset:
140–143h
Reset Value:
00010005h
Access:
RO-V, RO
Size:
32 bits
Bit
Access
Reset
Value
RST/
PWR
Description
31:20
RO
0h
Reserved (RSVD)
19:16
RO
1h
Uncore
Link Declaration Capability Version (LDCV)
Hardwired to 1 to indicate compliances with the 1.1 version of
Hardwired to 1 to indicate compliances with the 1.1 version of
the PCI Express specification.
Note: This version does not change for 2.0 compliance.
Note: This version does not change for 2.0 compliance.
15:0
RO
0005h
Uncore
Extended Capability ID (ECID)
Value of 0005 h identifies this linked list item (capability
Value of 0005 h identifies this linked list item (capability
structure) as being for PCI Express Link Declaration Capability.
See corresponding Egress Port Link Declaration Capability
See corresponding Egress Port Link Declaration Capability
registers for diagram of Link Declaration Topology.