Справочник Пользователя для HP A2Y15AV

126

Datasheet, Volume 2

This register provides information about PCI Express* Root Complex specific 
parameters.

31:18

RO

0h

17

RO

0b

Uncore

PME Pending (PMEP) 
This bit indicates that another PME is pending when the PME 

Status bit is set. When the PME Status bit is cleared by software, 

the PME is delivered by hardware by setting the PME Status bit 

again and updating the Requestor ID appropriately. The PME 

pending bit is cleared by hardware if no more PMEs are pending.

16

RW1C

0b

Uncore

PME Status (PMES) 
This bit indicates that PME was asserted by the requestor ID 

indicated in the PME Requestor ID field. Subsequent PMEs are 

kept pending until the status register is cleared by writing a 1 to 

this field.
An interrupt is asserted if PMEIE is asserted and PMES is 

changing from 0 to 1.
An interrupt is deasserted if PMEIE is asserted and PMES is 

changing from 1 to 0.
An Assert_PMEGPE is sent upstream if PMEGPEE in PEG Legacy 

Control register (PEGLC) is asserted and PMES is changing from 0 

to 1.
A Deassert_PMEGPE is sent upstream if PMEGPEE in PEG Legacy 

Control register (PEGLC) is asserted and PMES is changing from 1 

to 0
An interrupt is deasserted if PMEIE is asserted and PMES is 

changing from 1 to 0. 

15:0

RO-V

0000h

Uncore

PME Requestor ID (PMERID) 
This field indicates the PCI requestor ID of the last PME 

requestor.