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Datasheet, Volume 2
137
Processor Configuration Registers 
2.7.6
VC0RSTS—VC0 Resource Status Register
This register reports the Virtual Channel specific status.
2.7.7
PEG_TC—PCI Express* Completion Timeout Register
This register reports PCI Express* configuration control of PCI Express Completion 
Timeout related parameters that are not required by the PCI Express specification.
B/D/F/Type:
0/1/0–2/MMR
Address Offset:
11A–11Bh
Reset Value:
0002h
Access:
RO-V
Size:
16 bits
BIOS Optimal Default
0000h
Bit
Access
Reset 
Value
RST/
PWR
Description
15:2
RO
0h
Reserved (RSVD) 
1
RO-V
1b
Uncore
VC0 Negotiation Pending (VC0NP)
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation 
(initialization or disabling).
This bit indicates the status of the process of Flow Control 
initialization. It is set by default on Reset, as well as whenever 
the corresponding Virtual Channel is Disabled or the Link is in the 
DL_Down state. It is cleared when the link successfully exits the 
FC_INIT2 state.
Before using a Virtual Channel, software must check whether the 
VC Negotiation Pending fields for that Virtual Channel are cleared 
in both Components on a Link.
0
RO
0h
Reserved (RSVD) 
B/D/F/Type:
0/1/0–2/MMR
Address Offset:
208h
Access:
RW
Bit
Access
Reset 
Value
RST/
PWR
Description
31:15
RO
000000000
00000000b
Reserved (RSVD)
14:12
RW
111b
PCI Express Completion Timeout (PEG_TC)
This field determines the number of milliseconds the Transaction 
Layer will wait to receive an expected completion. To avoid hang 
conditions, the Transaction Layer will generate a dummy 
completion to the requestor if it does not receive the completion 
within this time period.
000 = Disable
001 = Reserved
010 = Reserved
100 = Reserved
101 = Reserved
110 = Reserved
x11 = 48 ms – for normal operation
11:0
RO
000000000
000b
Reserved (RSVD)