Справочник Пользователя для HP A2Y15AV
Processor Configuration Registers
150
Datasheet, Volume 2
2.8.3
PCICMD2—PCI Command Register
This 16-bit register provides basic control over the IGD's ability to respond to PCI
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
cycles. The PCICMD Register in the IGD disables the IGD PCI compliant master
accesses to main memory.
B/D/F/Type:
0/2/0/PCI
Address Offset:
4–5h
Reset Value:
0000h
Access:
RW, RO
Size:
16 bits
BIOS Optimal Default
00h
Bit
Access
Reset
Value
RST/
PWR
Description
15:11
RO
0h
Reserved (RSVD)
10
RW
0b
FLR,
Uncore
Interrupt Disable (INTDIS)
This bit disables the device from asserting INTx#.
0 = Enable the assertion of this device's INTx# signal.
1 = Disable the assertion of this device's INTx# signal. DO_INTx
This bit disables the device from asserting INTx#.
0 = Enable the assertion of this device's INTx# signal.
1 = Disable the assertion of this device's INTx# signal. DO_INTx
messages will not be sent to DMI.
9
RO
0b
Uncore
Fast Back-to-Back (FB2B)
Not Implemented. Hardwired to 0.
Not Implemented. Hardwired to 0.
8
RO
0b
Uncore
SERR Enable (SERRE)
Not Implemented. Hardwired to 0.
Not Implemented. Hardwired to 0.
7
RO
0b
Uncore
Address/Data Stepping Enable (ADSTEP)
Not Implemented. Hardwired to 0.
Not Implemented. Hardwired to 0.
6
RO
0b
Uncore
Parity Error Enable (PERRE)
Not Implemented. Hardwired to 0. Since the IGD belongs to the
Not Implemented. Hardwired to 0. Since the IGD belongs to the
category of devices that does not corrupt programs or data in
system memory or hard drives, the IGD ignores any parity error
that it detects and continues with normal operation.
5
RO
0b
Uncore
Video Palette Snooping (VPS)
This bit is hardwired to 0 to disable snooping.
This bit is hardwired to 0 to disable snooping.
4
RO
0b
Uncore
Memory Write and Invalidate Enable (MWIE)
Hardwired to 0. The IGD does not support memory write and
Hardwired to 0. The IGD does not support memory write and
invalidate commands.
3
RO
0b
Uncore
Special Cycle Enable (SCE)
This bit is hardwired to 0. The IGD ignores Special cycles.
This bit is hardwired to 0. The IGD ignores Special cycles.
2
RW
0b
FLR,
Uncore
Bus Master Enable (BME)
0 = Disable IGD bus mastering.
1 = Enable the IGD to function as a PCI compliant master.
0 = Disable IGD bus mastering.
1 = Enable the IGD to function as a PCI compliant master.
1
RW
0b
FLR,
Uncore
Memory Access Enable (MAE)
This bit controls the IGD's response to memory space accesses.
0 = Disable.
1 = Enable.
This bit controls the IGD's response to memory space accesses.
0 = Disable.
1 = Enable.
0
RW
0b
FLR,
Uncore
I/O Access Enable (IOAE)
This bit controls the IGD's response to I/O space accesses.
0 = Disable.
1 = Enable.
This bit controls the IGD's response to I/O space accesses.
0 = Disable.
1 = Enable.