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Processor Configuration Registers
158
Datasheet, Volume 2
2.8.17
INTRLINE—Interrupt Line Register
This 8-bit register is used to communicate interrupt line routing information. It is 
read/write and must be implemented by the device. POST software will write the 
routing information into this register as it initializes and configures the system.
The value in this register tells which input of the system interrupt controller(s) the 
device's interrupt pin is connected to. The device itself does not use this value; rather it 
is used by device drivers and operating systems to determine priority and vector 
information.
2.8.18
INTRPIN—Interrupt Pin Register
This register tells which interrupt pin the device uses. The Integrated Graphics Device 
uses INTA#.
2.8.19
MINGNT—Minimum Grant Register
The Integrated Graphics Device has no requirement for the settings of Latency Timers.
B/D/F/Type:
0/2/0/PCI
Address Offset:
3Ch
Reset Value:
00h
Access:
RW
Size:
8 bits
Bit
Access
Reset 
Value
RST/
PWR
Description
7:0
RW
00h
Uncore
Interrupt Connection (INTCON) 
This field is used to communicate interrupt line routing 
information. POST software writes the routing information into 
this register as it initializes and configures the system. The value 
in this register indicates to which input of the system interrupt 
controller the device's interrupt pin is connected.
B/D/F/Type:
0/2/0/PCI
Address Offset:
3Dh
Reset Value:
01h
Access:
RO
Size:
8 bits
Bit
Access
Reset 
Value
RST/
PWR
Description
7:0
RO
01h
Uncore
Interrupt Pin (INTPIN) 
As a single function device, the IGD specifies INTA# as its 
interrupt pin.
01h = INTA#.
B/D/F/Type:
0/2/0/PCI
Address Offset:
3Eh
Reset Value:
00h
Access:
RO
Size:
8 bits
Bit
Access
Reset 
Value
RST/
PWR
Description
7:0
RO
00h
Uncore
Minimum Grant Value (MGV) 
The IGD does not burst as a PCI compliant master.