Справочник Пользователя для HP A2Y15AV

Скачать
Страница из 342
Processor Configuration Registers
168
Datasheet, Volume 2
2.10.6
CC—Class Code Register
This register identifies the basic function of the device, a more specific sub-class, and a 
register- specific programming interface.
2.10.7
CL—Cache Line Size Register
2.10.8
HDR—Header Type Register
B/D/F/Type:
0/6/0/PCI
Address Offset:
9–Bh
Reset Value:
060400h
Access:
RO
Size:
24 bits
Bit
Access
Reset 
Value
RST/
PWR
Description
23:16
RO
06h
Uncore
Base Class Code (BCC) 
Indicates the base class code for this device. This code has the 
value 06h indicating a Bridge device. 
15:8
RO
04h
Uncore
Sub-Class Code (SUBCC) 
Indicates the sub-class code for this device. The code is 04h 
indicating a PCI to PCI Bridge. 
7:0
RO
00h
Uncore
Programming Interface (PI) 
Indicates the programming interface of this device. This value 
does not specify a particular register set layout and provides no 
practical use for this device. 
B/D/F/Type:
0/6/0/PCI
Address Offset:
Ch
Reset Value:
00h
Access:
RW
Size:
8 bits
Bit
Access
Reset 
Value
RST/
PWR
Description
7:0
RW
00h
Uncore
Cache Line Size (CLS)
Implemented by PCI Express devices as a read-write field for 
legacy compatibility purposes but has no impact on any PCI 
Express device functionality. 
B/D/F/Type:
0/6/0/PCI
Address Offset:
Eh
Reset Value:
81h
Access:
RO
Size:
8 bits
Bit
Access
Reset 
Value
RST/
PWR
Description
7:0
RO
81h
Uncore
Header Type Register (HDR) 
Device 1 returns 81h to indicate that this is a multi function 
device with bridge header layout. 
Device 6 returns 01h to indicate that this is a single function 
device with bridge header layout.