Справочник Пользователя для HP A2Y15AV

Datasheet, Volume 2

207

Processor Configuration Registers 

This register controls the resources associated with PCI Express* Virtual Channel 0.

31

RO

1b

Uncore

VC0 Enable (VC0E)
For VC0 this is hardwired to 1 and read only as VC0 can never be 

disabled.

30:27

RO

0h

26:24

RO

000b

Uncore

VC0 ID (VC0ID): 
Assigns a VC ID to the VC resource. For VC0 this is hardwired to 

0 and read only.

23:20

RO

0h

19:17

RW

000b

Uncore

Port Arbitration Select (PAS)
Port Arbitration Select – This field configures the VC resource to 

provide a particular Port Arbitration service. This field is valid for 

RCRBs, Root Ports that support peer to peer traffic, and Switch 

Ports, but not for PCI Express Endpoint devices or Root Ports that 

do not support peer to peer traffic. 
The permissible value of this field is a number corresponding to 

one of the asserted bits in the Port Arbitration Capability field of 

the VC resource.
This field does not affect the root port behavior. 

16

RO

0h

15:8

RW

00h

Uncore

TC High VC0 Map (TCHVC0M): 
Allow usage of high order TCs.
BIOS should keep this field zeroed to allow usage of the reserved 

TC[3] for other purposes

7:1

RW

7Fh

Uncore

TC/VC0 Map (TCVC0M)
Indicates the TCs (Traffic Classes) that are mapped to the VC 

resource. Bit locations within this field correspond to TC values. 

For example, when bit 7 is set in this field, TC7 is mapped to this 

VC resource. When more than one bit in this field is set, it 

indicates that multiple TCs are mapped to the VC resource. In 

order to remove one or more TCs from the TC/VC Map of an 

enabled VC, software must ensure that no new or outstanding 

transactions with the TC labels are targeted at the given Link.

0

RO

1b

Uncore

TC0/VC0 Map (TC0VC0M)
Traffic Class 0 is always routed to VC0.