Справочник Пользователя для HP A2Y15AV
Datasheet, Volume 2
213
Processor Configuration Registers
2.11.15 PEGTST—PCI Express* Test Modes Register
2.11.16 PEGUPDNCFG—PEG UPconfig/DNconfig Control Register
This register allows software to dynamically limit the port width.
The sequence to change width is:
1. Write to this register the required width
2. Set Retrain link bit [5] in LCTL register
3. Wait till LSTS.LTRN [11] is clear
2. Set Retrain link bit [5] in LCTL register
3. Wait till LSTS.LTRN [11] is clear
Note:
Actual width may be lower due to card limitation.
B/D/F/Type:
0/6/0/MMR
Address Offset:
D0C–D0Fh
Reset Value:
00000000h
Access:
RO-FW, RW
Size:
32 bits
BIOS Optimal Default
0000000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:21
RO
0h
Reserved (RSVD)
20
RO-FW
0b
Uncore
PEG Lane Reversal Strap Status (LANEREVSTS)
This register bit reflects the status of the PEG lane reversal strap.
This register bit reflects the status of the PEG lane reversal strap.
The PEGLaneReversal strap is mirrored in this register bit.
0 = PEG lane is not reversed.
1 = PEG lane is reversed.
This bit is applicable only for Function 0 in Devices 1 and 6.
0 = PEG lane is not reversed.
1 = PEG lane is reversed.
This bit is applicable only for Function 0 in Devices 1 and 6.
Note:
Lane reversal is done end-to-end regardless of
bifurcation mode or not.
19:0
RO
0h
Reserved (RSVD)
B/D/F/Type:
0/6/0/MMR
Address Offset:
D34–D37h
Reset Value:
0000001Fh
Access:
RW, RW1CS
Size:
32 bits
BIOS Optimal Default
0000000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:7
RO
0h
Reserved (RSVD)
6
RW
0b
Uncore
Advertise Upconfig Capability (ADUPCFG)
0 = Do not advertise Upconfig support.
1 = Set the upconfig capable bit to 1 in our transmitted TS2s
0 = Do not advertise Upconfig support.
1 = Set the upconfig capable bit to 1 in our transmitted TS2s
during Config.Complete.
5:0
RO
0h
Reserved (RSVD)