Справочник Пользователя для HP A2Y15AV
Datasheet, Volume 2
219
Processor Configuration Registers
2.12.2
DMIPVCCAP1—DMI Port VC Capability Register 1
This register describes the configuration of PCI Express* Virtual Channels associated
with this port.
with this port.
2.12.3
DMIPVCCAP2—DMI Port VC Capability Register 2
This register describes the configuration of PCI Express* Virtual Channels associated
with this port.
with this port.
B/D/F/Type:
0/0/0/DMIBAR
Address Offset:
4–7h
Reset Value:
00000000h
Access:
RO, RW-O
Size:
32 bits
BIOS Optimal Default
0000000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:7
RO
0h
Reserved (RSVD)
6:4
RO
000b
Uncore
Low Priority Extended VC Count (LPEVCC)
This field indicates the number of (extended) Virtual Channels in
This field indicates the number of (extended) Virtual Channels in
addition to the default VC belonging to the low-priority VC (LPVC)
group that has the lowest priority with respect to other VC
resources in a strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.
The value of 0 in this field implies strict VC arbitration.
3
RO
0h
Reserved (RSVD)
2:0
RW-O
000b
Uncore
Extended VC Count (EVCC)
This field indicates the number of (extended) Virtual Channels in
This field indicates the number of (extended) Virtual Channels in
addition to the default VC supported by the device.
B/D/F/Type:
0/0/0/DMIBAR
Address Offset:
8–Bh
Reset Value:
00000000h
Access:
RO
Size:
32 bits
BIOS Optimal Default
0000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:24
RO
00h
Uncore
Reserved for VC Arbitration Table Offset (VCATO)
23:8
RO
0h
Reserved (RSVD)
7:0
RO
00h
Uncore
Reserved for VC Arbitration Capability (VCAC)