Справочник Пользователя для HP A2Y15AV
Processor Configuration Registers
228
Datasheet, Volume 2
2.12.16 DMIVCMRSTS—DMI VCm Resource Status Register
2.12.17 DMIRCLDECH—DMI Root Complex Link Declaration
Register
This capability declares links from the respective element to other elements of the root
complex component to which it belongs and to an element in another root complex
component. See PCI Express* specification for link/topology declaration requirements.
complex component to which it belongs and to an element in another root complex
component. See PCI Express* specification for link/topology declaration requirements.
B/D/F/Type:
0/0/0/DMIBAR
Address Offset:
3E–3Fh
Reset Value:
0002h
Access:
RO-V
Size:
16 bits
BIOS Optimal Default
0000h
Bit
Access
Reset
Value
RST/
PWR
Description
15:2
RO
0h
Reserved (RSVD)
1
RO-V
1b
Uncore
Virtual Channel Negotiation Pending (VCNEGPND)
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
(initialization or disabling).
Software may use this bit when enabling or disabling the VC. This
bit indicates the status of the process of Flow Control
initialization. It is set by default on Reset, as well as whenever
the corresponding Virtual Channel is Disabled or the Link is in the
DL_Down state. It is cleared when the link successfully exits the
FC_INIT2 state.
Before using a Virtual Channel, software must check whether the
Before using a Virtual Channel, software must check whether the
VC Negotiation Pending fields for that Virtual Channel are cleared
in both Components on a Link.
0
RO
0h
Reserved (RSVD)
B/D/F/Type:
0/0/0/DMIBAR
Address Offset:
40–43h
Reset Value:
08010005h
Access:
RO
Size:
32 bits
Bit
Access
Reset
Value
RST/
PWR
Description
31:20
RO
080h
Uncore
Pointer to Next Capability (PNC)
This field contains the offset to the next PCI Express capability
This field contains the offset to the next PCI Express capability
structure in the linked list of capabilities (Internal Link Control
Capability).
19:16
RO
1h
Uncore
Link Declaration Capability Version (LDCV)
Hardwired to 1 to indicate compliances with the 1.1 version of
Hardwired to 1 to indicate compliances with the 1.1 version of
the PCI Express specification.
Note: This version does not change for 2.0 compliance.
Note: This version does not change for 2.0 compliance.
15:0
RO
0005h
Uncore
Extended Capability ID (ECID)
a value of 0005h identifies this linked list item (capability
a value of 0005h identifies this linked list item (capability
structure) as being for PCI Express Link Declaration Capability.