Справочник Пользователя для HP A2Y15AV

234

Datasheet, Volume 2

This register allows control of PCI Express* link.

11:10

RO

11b

Uncore

Active State Link PM Support (ASLPMS) 
L0s & L1 entry supported.

9:4

RO

04h

Uncore

Max Link Width (MLW) 
This field indicates the maximum number of lanes supported for 

this link.

3:0

RW-OV

0001b

Uncore

Max Link Speed (MLS) 
This Reset Value reflects gen1.
Later the field may be changed by BIOS to allow gen2 subject to 

Fuse enabled.
Defined encodings are:
0001b = 2.5 GT/s Link speed supported
0010b = 5.0 GT/s and 2.5 GT/s Link speeds supported

15:10

RO

0h

9

RW

0b

Uncore

Hardware Autonomous Width Disable (HAWD)
When set, this bit disables hardware from changing the Link 

width for reasons other than attempting to correct unreliable Link 

operation by reducing Link width. 
Devices that do not implement the ability autonomously to 

change Link width are permitted to hardwire this bit to 0b. 

8

RO

0h

7

RW

0b

Uncore

Extended Synch (ES) 
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when 

exiting the L0s state and when in the Recovery state. 

This mode provides external devices (such as logic analyzers) 

monitoring the Link time to achieve bit and symbol lock before 

the link enters L0 and resumes communication. 
This is a test mode only and may cause other undesired side 

effects such as buffer overflows or underruns.

6

RO

0h

5

RW-V

0b

Uncore

Retrain Link (RL)
0 = Normal operation. 
1 = Full Link retraining is initiated by directing the Physical Layer 

LTSSM from L0, L0s, or L1 states to the Recovery state.

This bit always returns 0 when read. This bit is cleared 

automatically (no need to write a 0).