Справочник Пользователя для HP A2Y15AV

238

Datasheet, Volume 2

5

RWS

0b

Powergood

Hardware Autonomous Speed Disable (HASD)
When set to 1b this bit disables hardware from changing the 

link speed for reasons other than attempting to correct 

unreliable link operation by reducing link speed.

4

RWS

0b

Powergood

Enter Compliance (EC)
Software is permitted to force a link to enter Compliance mode 

at the speed indicated in the Target Link Speed field by setting 

this bit to 1b in both components on a link and then initiating a 

hot reset on the link.

3:0

RWS

2h

Powergood

Target Link Speed (TLS)
For Downstream ports, this field sets an upper limit on link 

operational speed by restricting the values advertised by the 

upstream component in its training sequences. 
0001b = 2.5 Gb/s Target Link Speed
0010b = 5 Gb/s Target Link Speed
All other encodings are reserved. 
If a value is written to this field that does not correspond to a 

speed included in the Supported Link Speeds field, the result is 

undefined. 
The Reset Value of this field is the highest link speed supported 

by the component (as reported in the Supported Link Speeds 

field of the Link Capabilities Register) unless the corresponding 

platform / form factor requires a different Reset Value. 
For both Upstream and Downstream ports, this field is used to 

set the target compliance mode speed when software is using 

the Enter Compliance bit to force a link into compliance mode. 

15:1

RO

0h

0

RO-V

0b

Uncore

Current De-emphasis Level (CURDELVL)
When the Link is operating at 5 GT/s speed, this reflects the level 

of de-emphasis.
1b = -3.5 dB
0b = -6 dB
When the Link is operating at 2.5 GT/s speed, this bit is 0b.