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Processor Configuration Registers
254
Datasheet, Volume 2
2.16.2
MAD_DIMM_ch0—Address Decode Channel 0 Register
This register defines channel characteristics – number of DIMMs, number of ranks, size, 
interleave options.
B/D/F/Type:
0/0/0/MCHBAR_MCMAIN
Address Offset:
5004–5007h
Reset Value:
00600000h
Access:
RW-L
Size:
32 bits
BIOS Optimal Default
00h
Bit
Access
Reset 
Value
RST/
PWR
Description
31:26
RO
0h
Reserved (RSVD) 
25:24
RO
00b
Reserved (RSVD) 
23
RO
0h
Reserved (RSVD) 
22
RW-L
1b
Uncore
Enhanced Interleave mode (Enh_Interleave) 
0 = off
1 = on
21
RW-L
1b
Uncore
Rank Interleave (RI) 
0 = off
1 = on
20
RW-L
0b
Uncore
DIMM B DDR width (DBW) 
0 = X8 chips
1 = X16 chips
19
RW-L
0b
Uncore
DIMM A DDR width (DAW) 
0 = X8 chips
1 = X16 chips
18
RW-L
0b
Uncore
DIMM B number of ranks (DBNOR) 
0 = single rank
1 = dual rank
17
RW-L
0b
Uncore
DIMM A number of ranks (DANOR) 
0 = single rank 
1 = dual rank
16
RW-L
0b
Uncore
DIMM A select (DAS) 
Selects which of the DIMMs is DIMM A – should be the larger 
DIMM:
0 = DIMM 0 
1 = DIMM 1
15:8
RW-L
00h
Uncore
Size of DIMM B (DIMM_B_Size) 
Size of DIMM B in 256 MB multiples
7:0
RW-L
00h
Uncore
Size of DIMM A (DIMM_A_Size) 
Size of DIMM A in 256 MB multiples