Справочник Пользователя для HP A2Y15AV
Processor Configuration Registers
278
Datasheet, Volume 2
2.18.10 FEDATA_REG—Fault Event Data Register
This register specifies the interrupt message data.
2.18.11 FEADDR_REG—Fault Event Address Register
This register specifies the interrupt message address.
2.18.12 FEUADDR_REG—Fault Event Upper Address Register
This register specifies the interrupt message upper address.
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
3C–3Fh
Reset Value:
00000000h
Access:
RW
Size:
32 bits
Bit
Access
Reset
Value
RST/
PWR
Description
31:16
RW
0000h
Uncore
Extended Interrupt Message Data (EIMD):
This field is valid only for implementations supporting 32-bit
This field is valid only for implementations supporting 32-bit
interrupt data fields.
Hardware implementations supporting only 16-bit interrupt data
Hardware implementations supporting only 16-bit interrupt data
may treat this field as RsvdZ.
15:0
RW
0000h
Uncore
Interrupt Message Data (IMD):
Data value in the interrupt request.
Data value in the interrupt request.
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
40–43h
Reset Value:
00000000h
Access:
RW
Size:
32 bits
BIOS Optimal Default
0h
Bit
Access
Reset
Value
RST/
PWR
Description
31:2
RW
00000000h
Uncore
Message Address (MA)
When fault events are enabled, the contents of this register
When fault events are enabled, the contents of this register
specify the DWord-aligned address (bits 31:2) for the interrupt
request.
1:0
RO
0h
Reserved (RSVD)
B/D/F/Type:
0/0/0/GFXVTBAR
Address Offset:
44–47h
Reset Value:
00000000h
Access:
RW
Size:
32 bits
Bit
Access
Reset
Value
RST/
PWR
Description
31:0
RW
00000000h
Uncore
Message upper address (MUA)
Hardware implementations supporting Extended Interrupt Mode
Hardware implementations supporting Extended Interrupt Mode
are required to implement this register.
Hardware implementations not supporting Extended Interrupt
Hardware implementations not supporting Extended Interrupt
Mode may treat this field as RsvdZ.