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Processor Configuration Registers
324
Datasheet, Volume 2
2.21.8
FSTS_REG—Fault Status Register
This register indicates the various error status.
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
34–37h
Reset Value:
00000000h
Access:
RW1CS, ROS-V, RO
Size:
32 bits
BIOS Optimal Default
00000h
Bit
Access
Reset 
Value
RST/
PWR
Description
31:16
RO
0h
Reserved (RSVD) 
15:8
ROS-V
00h
Powergood
Fault Record Index (FRI) 
This field is valid only when the PPF field is set.
The FRI field indicates the index (from base) of the fault 
recording register to which the first pending fault was recorded 
when the PPF field was set by hardware.
The value read from this field is undefined when the PPF field is 
clear.
7
RO
0h
Reserved (RSVD) 
6
RO
0b
Uncore
Invalidation Time-out Error (ITE) 
Hardware detected a Device-IOTLB invalidation completion 
time-out. At this time, a fault event may be generated based on 
the programming of the Fault Event Control register.
Hardware implementations not supporting device Device-
IOTLBs implement this bit as RsvdZ.
5
RO
0b
Uncore
Invalidation Completion Error (ICE) 
Hardware received an unexpected or invalid Device-IOTLB 
invalidation completion. This could be due to either an invalid 
ITag or invalid source-id in an invalidation completion response. 
At this time, a fault event may be generated based on the 
programming of the Fault Event Control register.
Hardware implementations not supporting Device-IOTLBs 
implement this bit as RsvdZ.
4
RW1CS
0b
Powergood
Invalidation Queue Error (IQE) 
Hardware detected an error associated with the invalidation 
queue. This could be due to either a hardware error while 
fetching a descriptor from the invalidation queue, or hardware 
detecting an erroneous or invalid descriptor in the invalidation 
queue. At this time, a fault event may be generated based on 
the programming of the Fault Event Control register.
Hardware implementations not supporting queued invalidations 
implement this bit as RsvdZ. 
3
RO
0b
Uncore
Advanced Pending Fault (APF) 
When this field is clear, hardware sets this field when the first 
fault record (at index 0) is written to a fault log. At this time, a 
fault event is generated based on the programming of the Fault 
Event Control register.
Software writing 1 to this field clears it. Hardware 
implementations not supporting advanced fault logging 
implement this bit as RsvdZ.