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Datasheet, Volume 2

331

Processor Configuration Registers 

This register sets up the limit address of DMA-protected low-memory region below 
4 GB. This register must be set up before enabling protected memory through 
PMEN_REG, and must not be updated when protected memory regions are enabled.

This register is always treated as RO for implementations not supporting protected low 
memory region (PLMR field reported as Clear in the Capability register).

The alignment of the protected low memory region limit depends on the number of 
reserved bits (N:0) of this register. Software may determine N by writing all 1s to this 
register, and finding most significant zero bit position with 0 in the value read back 
from the register. Bits N:0 of the limit register is decoded by hardware as all 1s.

The Protected low-memory base and limit registers functions as follows:

• Programming the protected low-memory base and limit registers with the same 

value in bits 31:(N+1) specifies a protected low-memory region of size 2^(N+1) 
bytes.

• Programming the protected low-memory limit register with a value less than the 

Protected low-memory base register disables the protected low-memory region.

Software must not modify this register when protected memory regions are enabled 
(PRS field set in PMEN_REG).

31:20

RW

000h

Uncore

Protected Low-Memory Limit (PLML) 
This register specifies the last host physical address of the DMA-

protected low-memory region in system memory.

19:0

RO

0h