Справочник Пользователя для HP A2Y15AV
Datasheet, Volume 2
67
Processor Configuration Registers
2.5.23
PAM2—Programmable Attribute Map 2 Register
This register controls the read, write and shadowing attributes of the BIOS range from
C_8000h to C_FFFFh. The Uncore allows programmable memory attributes on 13
legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven
Programmable Attribute Map (PAM) registers are used to support these features.
Cacheability of these areas is controlled using the MTRR register in the core.
C_8000h to C_FFFFh. The Uncore allows programmable memory attributes on 13
legacy memory segments of various sizes in the 768 KB to 1 MB address range. Seven
Programmable Attribute Map (PAM) registers are used to support these features.
Cacheability of these areas is controlled using the MTRR register in the core.
Two bits are used to specify memory attributes for each memory segment. These bits
apply to host accesses to the PAM areas. These attributes are:
apply to host accesses to the PAM areas. These attributes are:
• RE – Read Enable. When RE=1, the host read accesses to the corresponding
memory segment are claimed by the Uncore and directed to main memory.
Conversely, when RE=0, the host read accesses are directed to DMI.
Conversely, when RE=0, the host read accesses are directed to DMI.
• WE – Write Enable. When WE=1, the host write accesses to the corresponding
memory segment are claimed by the Uncore and directed to main memory.
Conversely, when WE=0, the host read accesses are directed to DMI.
Conversely, when WE=0, the host read accesses are directed to DMI.
The RE and WE attributes permit a memory segment to be Read Only, Write Only,
Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the
segment is Read Only.
Read/Write or Disabled. For example, if a memory segment has RE=1 and WE=0, the
segment is Read Only.
B/D/F/Type:
0/0/0/PCI
Address Offset:
82h
Reset Value:
00h
Access:
RW
Size:
8 bits
BIOS Optimal Default
0h
Bit
Access
Reset
Value
RST/
PWR
Description
7:6
RO
0h
Reserved (RSVD)
5:4
RW
00b
Uncore
0CC000–0CFFFF Attribute (HIENABLE)
This field controls the steering of read and write cycles that
This field controls the steering of read and write cycles that
address the BIOS area from 0CC000h to 0CFFFFh.
00 = DRAM Disabled. All accesses are directed to DMI.
01 = Read Only. All reads are sent to DRAM, all writes are
00 = DRAM Disabled. All accesses are directed to DMI.
01 = Read Only. All reads are sent to DRAM, all writes are
forwarded to DMI.
10 = Write Only. All writes are sent to DRAM, all reads are
serviced by DMI.
11 = Normal DRAM Operation. All reads and writes are serviced
by DRAM.
This register is locked by Intel TXT.
3:2
RO
0h
Reserved (RSVD)
1:0
RW
00b
Uncore
0C8000–0CBFFF Attribute (LOENABLE)
This field controls the steering of read and write cycles that
This field controls the steering of read and write cycles that
address the BIOS area from 0C8000h to 0CBFFFh.
00 = DRAM Disabled. All reads are sent to DRAM. All writes are
00 = DRAM Disabled. All reads are sent to DRAM. All writes are
forwarded to DMI.
01 = Read Only. All reads are sent to DRAM. All writes are
forwarded to DMI.
10 = Write Only. All writes are sent to DRAM. All reads are
serviced by DMI.
11 = Normal DRAM Operation. All reads and writes are serviced
by DRAM.
This register is locked by Intel TXT.