Справочник Пользователя для HP A2Y15AV

80

Datasheet, Volume 2

This register contains the base address of TSEG DRAM memory. BIOS determines the 
base of TSEG memory which must be at or below Graphics Base of GTT Stolen Memory 
(PCI Device 0 Offset B4h bits 31:20).

BIOS must program TSEGMB to an 8 MB naturally aligned boundary.

This 32 bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics memory 
and Graphics Stolen Memory are within the DRAM space defined. From the top, the 
Host optionally claims 1 to 64 MB of DRAM for internal graphics if enabled, 1 or 2 MB of 
DRAM for GTT Graphics Stolen Memory (if enabled) and 1, 2, or 8 MB of DRAM for TSEG 
if enabled.

Programming Example:

C1DRB3 is set to 4 GB
TSEG is enabled and TSEG size is set to 1 MB
Internal Graphics is enabled, and Graphics Mode Select is set to 32 MB
GTT Graphics Stolen Memory Size set to 2 MB
BIOS knows the OS requires 1 GB of PCI space.
BIOS also knows the range from 0_FEC0_0000h to 0_FFFF_FFFFh is not usable 

by the system. This 20 MB range at the very top of addressable memory space 
is lost to APIC and Intel TXT.

According to the above equation, TOLUD is originally calculated to:  

4 GB = 1_0000_0000h

The system memory requirements are:  

4 GB (max addressable space) – 1G B (PCI space) – 35 MB (lost memory) = 3 GB – 
35 MB (minimum granularity) = 0_ECB0_0000h

Since 0_ECB0_0000h (PCI and other system requirements) is less than 
1_0000_0000h, TOLUD should be programmed to ECBh.

These bits are Intel TXT lockable.

31:20

RW-L

000h

Uncore

TESG Memory base (TSEGMB) 
This register contains the base address of TSEG DRAM memory. 

BIOS determines the base of TSEG memory which must be at or 

below Graphics Base of GTT Stolen Memory (PCI Device 0 Offset 

B4h bits 31:20).

19:1

RO

0h

0

RW-KL

0b

Uncore

Lock (LOCK) 
This bit will lock all writeable settings in this register, including 

itself.