Справочник Пользователя для Intel G550T CM8062301002309
Модели
CM8062301002309
Processor Configuration Registers
124
Datasheet, Volume 2
6
RWS
0b
Powerg
ood
Selectable De-emphasis (selectabledeemphasis)
When the Link is operating at 5GT/s speed, selects the level of de-
When the Link is operating at 5GT/s speed, selects the level of de-
emphasis. Encodings:
1 = -3.5 dB
0 = -6 dB
Reset Value is implementation specific, unless a specific value is
0 = -6 dB
Reset Value is implementation specific, unless a specific value is
required for a selected form factor or platform.
When the Link is operating at 2.5 GT/s speed, the setting of this bit
When the Link is operating at 2.5 GT/s speed, the setting of this bit
has no effect. Components that support only the 2.5 GT/s speed
are permitted to hardwire this bit to 0b.
5
RO
0h
Reserved
4
RWS
0b
Powerg
ood
Enter Compliance (EC)
Software is permitted to force a link to enter Compliance mode at
Software is permitted to force a link to enter Compliance mode at
the speed indicated in the Target Link Speed field by setting this bit
to 1b in both components on a link and then initiating a hot reset
on the link.
3:0
RWS
2h
Powerg
ood
Target Link Speed (TLS)
For Downstream ports, this field sets an upper limit on link
For Downstream ports, this field sets an upper limit on link
operational speed by restricting the values advertised by the
upstream component in its training sequences.
Defined encodings are:
0001 = 2.5 Gb/s Target Link Speed
0010 = 5Gb/s Target Link Speed
All other encodings are reserved.
If a value is written to this field that does not correspond to a
Defined encodings are:
0001 = 2.5 Gb/s Target Link Speed
0010 = 5Gb/s Target Link Speed
All other encodings are reserved.
If a value is written to this field that does not correspond to a
speed included in the Supported Link Speeds field, the result is
undefined.
The Reset Value of this field is the highest link speed supported by
The Reset Value of this field is the highest link speed supported by
the component (as reported in the Supported Link Speeds field of
the Link Capabilities Register) unless the corresponding platform /
form factor requires a different Reset Value.
For both Upstream and Downstream ports, this field is used to set
For both Upstream and Downstream ports, this field is used to set
the target compliance mode speed when software is using the
Enter Compliance bit to force a link into compliance mode.
B/D/F/Type:
0/1/0–2/PCI
Address Offset:
D0–D1h
Reset Value:
0002h
Access:
RWS, RWS-V
Size:
16 bits
BIOS Optimal Default
0h
Bit
Attr
Reset
Value
RST/
PWR
Description