Справочник Пользователя для Hitachi 100GB 7200 RPM HTE721010G9SA00

Travelstar E7K100 (Serial ATA) Hard Disk Drive Specification

42 

This register contains the command code being sent to the device. Command execution begins immediately after 
this register is written. 

All other registers required for the command must be set up before writing the Command Register.

This register contains the device and head numbers. 

Device Control Register

7

6

5

4

3

2

1

0

-

-

-

-

1

SRST

-IEN

0

Software Reset. The device is held reset when RST=1. Setting 

RST=0 re-enables the device. 

The host must set RST=1 and wait for at least 5 microseconds 

before setting RST=0, to ensure that the device recognizes the 

resest. 

Interrupt Enable. When IEN=0, and the device is selected, device 

interurupts to the host will be enabled. When IEN=1, or the 

device is not selected, device interrupts to the host will be 

disabled. 

Device Control Register

7

6

5

4

3

2

1

0

-

L

-

0

HS3

HS2

HS1

HS0

Binary encoded address mode select. When L=0, addressing is by 

CHS mode. When L=1, addressing is by LBA mode. 

The HS3 through HSO contain bits 24-27 of the LBA. At command 

completion, these bits are updated to reflect the current LBA 

bits 24-27.