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PCU – iLB – Low Pin Count (LPC) Bridge
1180
Datasheet
24
PCU – iLB – Low Pin Count 
(LPC) Bridge
The processor implements an LPC Interface as described in the LPC 1.1 Specification. 
The Low Pin Count (LPC) bridge function of the processor resides in PCI Device 31, 
Function 0.
Note:
In addition to the LPC bridge interface function, D31:F0 contains other functional units 
including interrupt controllers, timers, power management, system management, 
GPIO, and RTC.
24.1
Signal Descriptions
See 
 for additional details.
The signal description table has the following headings:
Signal Name: The name of the signal/pin
Direction: The buffer direction can be either input, output, or I/O (bidirectional)
Type: The buffer type found in 
Description: A brief explanation of the signal’s function
I
O
I
O
I
O
I
O
I
O
I
O
I
O
O
Platform Control Unit
UART
LP
C
GP
IO
RTC
HP
ET
82
59
AP
IC
82
54
SMB
iLB
SPI
PM
C