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Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
169
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.7.1.2
MEM_ACCUMULATED_BW_CH_[0:3]
This register contains a measurement proportional to the weighted DRAM BW for the 
channel including all ranks. The weights are configured in the memory controller 
channel register PM_CMD_PWR.
13.7.1.3
PACKAGE_POWER_SKU
Defines allowed SKU power and timing parameters.
7:0
RO_V
0x0
Channel 0 Maximum Temperature (Channel0_Max_Temperature):
Temperature in Degrees (C).
Type:
CFG
PortID: N/A
Bus:
1
Device: 10
Function:
0
Offset:
0x60
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
1
Device:
10Function:0
Offset:
0x64, 0x68, 0x6c, 0x70
Bit
Attr
Default
Description
31:0
RO_V
0x0
Data (DATA):
The weighted BW value is calculated by the memory controller based on the 
following formula:
NumPrecharge * PM_CMD_PWR[PWR_RAS_PRE] +
NumReads * PM_CMD_PWR[PWR_CAS_R] +
NumWrites * PM_CMD_PWR[PWR_CAS_W]
Type:
CFG
PortID: N/A
Bus:
1
Device: 10
Function:
0
Offset:
0x84
Bit
Attr
Default
Description
63:55
RV
-
Reserved.
54:48
RO_V
0x2f
Maximal Time Window (PKG_MAX_WIN):
The maximum allowed time window for a processor that could be used in 
various power limit MSRs. 
Package Max Time = (float) (1+ X/4) * (2 ^ Y)* (time unit) 
Where 
X = PACKAGE_MAX_TIME [54:53] 
Y = PACKAGE_MAX_TIME [52:48] The unit of measurement for this field is 
defined in the TIME_UNIT field in the PACKAGE_POWER_SKU_UNIT register. 
Note: For some processors, this value may be 0 indicating that there is no limit 
on time window to be programmed in PACKAGE_POWER_LIMIT MSR and 
PP0_POWER_LIMIT MSR. 
47:47
RV
-
Reserved.
46:32
RO_V
Varies
Maximal Package Power (PKG_MAX_PWR):
The maximum allowed power limit for a processor that could be used in the 
PACKAGE_POWER_LIMIT register. The value is in the units identified in 
POWER_UNIT field in PACKAGE_POWER_SKU_UNIT resistor. 
31:31
RV
-
Reserved.