Справочник Пользователя для Intel E7-8891 v2 CM8063601377422

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Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
175
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.7.3.1
PACKAGE_RAPL_PERF_STATUS
This register is used by PCU microcode to report Package Power limit violations in the 
Platform PBM.
13.7.3.2
DRAM_POWER_INFO
Defines allowed DRAM power and timing parameters.
PCU microcode will update the contents of this register.
Type:
CFG
PortID: N/A
Bus:
1
Device: 10
Function:
2
Offset:
0x88
Bit
Attr
Default
Description
31:0
RO_V
0x0
Power Limit Throttle Counter (PWR_LIMIT_THROTTLE_CTR):
Reports the number of times the Power limiting algorithm had to clip the power 
limit due to hitting the lowest power state available.
Accumulated PACKAGE throttled time
Type:
CFG
PortID: N/A
Bus:
1
Device: 10
Function:
2
Offset:
0x90
Bit
Attr
Default
Description
63:63
RW_KL
0x0
Lock:
Lock bit to lock the Register
62:55
RV
-
Reserved.
54:48
RW_L
0x28
Maximal Time Window (DRAM_MAX_WIN):
The maximal time window allowed for the DRAM. Higher values will be clamped 
to this value.
 
 x = PKG_MAX_WIN[54:53]
 y = PKG_MAX_WIN[52:48]
 
 The timing interval window is Floating Point number given by 1.x * power 
(2,y).
 
 The unit of measurement is defined in 
DRAM_POWER_INFO_UNIT_MSR[TIME_UNIT].
47:47
RV
-
Reserved.
46:32
RW_L
0x258
Maximal Package Power (DRAM_MAX_PWR):
The maximal power setting allowed for DRAM. Higher values will be clamped to 
this value. The maximum setting is typical (not guaranteed).
 The units for this value are defined in 
DRAM_POWER_INFO_UNIT_MSR[PWR_UNIT].
31:31
RV
-
Reserved.
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