Справочник Пользователя для Intel E7-8891 v2 CM8063601377422
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CM8063601377422
Cbo Functional Description
32
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
3.2.3.1
SAD Decoders and Priority
There are a total of four types of decoders in the SAD. Each of them covers a
different part of the address map. These decoders do sometimes overlap, with explicit
priorities defined for the cases when matches in multiple decoders occur in parallel so
that we can ensure no holes in the address map exist. Below are the four types of
decoders in SAD:
different part of the address map. These decoders do sometimes overlap, with explicit
priorities defined for the cases when matches in multiple decoders occur in parallel so
that we can ensure no holes in the address map exist. Below are the four types of
decoders in SAD:
• DRAM decoders: These are the decoders used to program DRAM configuration in
the system.
• MMIO decoder: These are decoders used to define MMIO-L and MMIO-H region.
• Interleave decoder: This is a special decoder to decode MMCFG region. It has up to
• Interleave decoder: This is a special decoder to decode MMCFG region. It has up to
8 interleave targets and can be configured to cover either the whole segment 0
region or some part of the higher segments in the case we have higher segments.
region or some part of the higher segments in the case we have higher segments.
• Legacy decoder: Used to define various legacy ranges.
3.2.4
DRAM/MMIO Decoders
3.2.4.1
DRAM Decoders
The Intel Xeon processor E7 v2 product family Cbo DRAM decoders will support 2, 4,
and 8 way interleaving. In Intel Xeon processor E7 v2 product family, we employ a
hierarchical address decode approach, therefore the way definition here corresponds to
a node ID as opposed to a channel in the memory itself. The Intel Xeon processor E7 v2
product family home agent handles channel interleaving internally.
and 8 way interleaving. In Intel Xeon processor E7 v2 product family, we employ a
hierarchical address decode approach, therefore the way definition here corresponds to
a node ID as opposed to a channel in the memory itself. The Intel Xeon processor E7 v2
product family home agent handles channel interleaving internally.
3.2.4.2
MMIO Decoders
MMIO decoders are very similar to DRAM decoders. The only difference is that MMIO
decoders do not require interleaving. Each range is designated toward one target as
opposed to a list of targets (that is, no interleaving).
decoders do not require interleaving. Each range is designated toward one target as
opposed to a list of targets (that is, no interleaving).
MMIO decoders covers the range of MMIO-L and MMIO-H in the system address map.
Intel Xeon processor E7 v2 product family supports 16 address match rules with MMIO
decoders and with granularity of 16 MB. This means that there can be up to 16 different
segments within MMIO-L and MMIO-H regions.
Intel Xeon processor E7 v2 product family supports 16 address match rules with MMIO
decoders and with granularity of 16 MB. This means that there can be up to 16 different
segments within MMIO-L and MMIO-H regions.
3.2.5
Legacy Decoder
The Legacy decoder outputs on of the following types:
1. HOM: the target lies in Coherent DRAM
2. CFG: the target is PCI configuration register. The Intel QPI opcodes are:
2. CFG: the target is PCI configuration register. The Intel QPI opcodes are:
NcCfgRd/NcCfgWr
3. LT: trusted register regions (not config): The Intel QPI opcodes are: NcLtRd/NcLtWr
4. MMIO: if none of the above rules applied, this is the default option that will be
4. MMIO: if none of the above rules applied, this is the default option that will be
decoded by MMIO decoders. The Intel QPI opcodes are: NcRd/NcWr{Ptl}
5. IO: IO space, The Intel QPI opcodes are: NcIoRd/NcIoWr
6. ABORT: Cbo would return data of all ‘1s for reads and complete writes (throw away
6. ABORT: Cbo would return data of all ‘1s for reads and complete writes (throw away
data) when abort is indicated by decoder.
7. NO_EGO region will be covered by MMIO-L. BIOS must program this properly by
ensuring MMIO decoder overlaps the NO_EGO region.