Справочник Пользователя для Intel E7-8891 v2 CM8063601377422

386

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

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dmi_vc1_vt_d_fetch_ordering:

This mode is to allow VC1 Intel

®

VT-d conflicts with outstanding VC0 

Intel

®

VT-d reads on IDI to be pipelined. This can occur when Intel

®

VT-d 

tables are shared between Intel

®

VT (VC1) and other devices. To ensure 

QoS the Intel

®

VT-d reads from VC1 need to be issued in parallel with non-

Isoc accesses to the same cacheline.

0: Serialize all IDI address conflicts to DRAM
1: Pipeline Intel

®

VT-d reads from VC1 with address conflict on IDI

Notes:
A maximum of 1 VC1 Intel

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VT-d read and 1 non-VC1 Intel

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VT-d read to 

the same address can be outstanding on IDI.

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pipeline_ns_writes_on_csi:

When set, allows inbound non-snooped writes to pipeline at the coherent 

interface - issuing the writes before previous writes are completed in the 

coherent domain.

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vc1_reads_bypass_writes:

0: VC1 Reads push VC1 writes
1: VC1 Reads are allowed to bypass VC1 writes

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lock_thaw_mode:

Mode controls how inbound queues in the south agents (PCIE, DMI) thaw 

when they are target of a locked read. See xref for details on when this 

should be used and on the restrictions in its use.

0: Thaw only posted requests
1: Thaw posted and non-posted requests.

Note that if the lock target is also a “problematic” port (as indicated by bit 

TBD in MISCCTRLSTS register), then this becomes meaningless because 

both posted and non-posted requests are thawed.

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RV

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Reserved.