Справочник Пользователя для Intel E7-8891 v2 CM8063601377422

390

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

24:24

RW_L

0x1

enable_vtd_reuse:

disregards the reuse hint from vtd. results in a fetch to CBO every time

23:22

RW_L

0x0

aging_timer_rollover:

0: disabled
1: 32us
2: 128us
3: 512us

There is an error of abt + 100%. numbers maybe moved around a little to 

facilitate presilicon validation

21:15

RW_L

0x3

threshold_to_flush_reusable_lines:

The number of free lines left before some of the older vtd reuse lines are 

flushed

14:14

RW_L

0x0

repeat_dumped_pf:

This is a performance optimization to quickly reissue a prefetch when 

ownership is lost due to a tickle. Specifically, if ownership is lost due to a 

tickle, it is reissued independent of the switch coming back without a fetch 

from switch.

Note:
This bit should never be set.

13:9

RW_L

0x9

min_free_cq_entries:

The number of free conflictq entries at which the non-isoc transactions are 

throttled. There are a total of 32 entries to begin with. Valid programming 

values are 0x0 to 0x1E.
0x1F is an invalid programming value and should not be used.

8:8

RW_L

0x1

check_iocfg_format:

does some format checking address alignment for io and cfg transactions.

7:7

RW_L

0x1

check_ltrd_format:

does some format checking for lt transactions.

6:6

RW_L

0x1

use_isoc_ovf_q:

use a different queue between switch and IRP for isoc transaction.

5:5

RW_L

0x1

enable_spl_isoc_vt_reqs:

issue an isoc Intel VT transaction irrespective of whether another trans to 

the same address is pending or not.

4:1

RW_L

0x4

min_free_isoc_hq_entry:

0:0

RV

0x0

Reserved: