Справочник Пользователя для Intel E7-8891 v2 CM8063601377422

450

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

IRP Protocol Error Control.

This register enables the error status bit setting for a Coherent Interface detected error. 
Setting of the bit enables the setting of the corresponding error status bit in IRPPERRST 
register. If the bit is cleared, the corresponding error status will not be set.

10:10

RW1CS

0x0

protocol_rcvd_unexprsp: (D7)

A completion has been received from the Coherent Interface that was 

unexpected.

9:5

RV

-

Reserved2:

Reserved

4:4

RW1CS

0x0

csr_acc_32b_unaligned: (C3):

CSR access crossing 32-bit boundary.

3:3

RW1CS

0x0

wrcache_uncecc_error: (C2)

A double bit ECC error was detected within the Write Cache.

2:2

RW1CS

0x0

protocol_rcvd_poison: (C1)

A poisoned packet has been received from the Coherent Interface.

1:1

RW1CS

0x0

wrcache_correcc_error: (B4)

A single bit ECC error was detected and corrected within the Write Cache.

0:0

RV

-

Reserved1:

Reserved

31:15

RV

-

Reserved4:

Reserved

14:14

RWS

0x0

protocol_parity_error: (DB)

0: Disable error status logging for this error
1: Enable Error status logging for this error

13:13

RWS

0x0

protocol_qt_overflow_underflow: (DA)

0: Disable error status logging for this error
1: Enable Error status logging for this error

12:11

RV

-

Reserved3:

Reserved