Справочник Пользователя для Intel E7-8891 v2 CM8063601377422

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

93

Datasheet Volume Two: Functional Description, February 2014

TAD Range Wayness, Limit and Target.

There are total of 12 TAD ranges (N + P + 1 = number of TAD ranges; P = how many 
times channel interleave changes within the SAD ranges.).

Note for mirroring configuration:

For 1-way interleave, channel 0-2 mirror pair: target list = <0,2,x,x>, 
TAD ways = “00”

11:10

RW_LB

0x0

CPGC_IOSAV (trng_mode):

00: IOSAV mode
01: CPGC Mode- Setting to be used post VMSE CMD training (including EV)
10: CPGC VMSE CMD training mode - Set until VMSE CMD (coarse/fine) bus 

is trained
11: Normal Mode

Converged Pattern Generation and Checking (CPGC) is described in the 

System Agent BIOS specification.

9:9

RV

-

Reserved2:

Reserved.

8:8

RW_LB

0x0

NORMAL (normal):

0: Training mode
1: Normal Mode

7:4

RV

-

Reserved1:

Reserved.

3:3

RW_LBV

0x0

DIR_EN (dir_en):

Should always be set with VMSE. It is important to know that changing this 

bit will require BIOS to reinitialize the memory.

2:2

RW_LBV

0x0

ECC_EN (ecc_en):

ECC enable.

Note: This bit may be overridden to 0 when disable ECC via fuse.

1:1

RW_LBV

0x0

LS_EN (ls_en):

Use lock-step channel mode if set; otherwise, independent channel mode. 
This field should only be set for native ddr3 lockstep.
VMSE Lockstep 1:1 mode should always set this bit to 0

Note: This bit will only work if the SKU is enabled for this feature.

0:0

RW_LB

0x0

CLOSE_PG (close_pg):

Use close page address mapping if set; otherwise, open page.