Справочник Пользователя для Intel E7-4850 v2 CM8063601272906

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

241

Datasheet Volume Two: Functional Description, February 2014

15:12

12:12 (Device 0 

Function 0)

RWS

0x0

compliance_de_emphasis:

For 8GT/s Data Rate:
This bit sets the Transmitter Preset level in Polling.Compliance 

state if the entry occurred due to the Enter Compliance bit 

being 1b. The Encodings are defined as follows:

0000b: -6 dB for deemphasis, 0 dB for preshoot
0001b: -3.5 dB for deemphasis, 0 dB for preshoot
0010b: -4.5 dB for deemphasis, 0 dB for preshoot
0011b: -2.5 dB for deemphasis, 0 dB for preshoot
0100b: 0 dB for deemphasis, 0 dB for preshoot
0101b: 0 dB for deemphasis, 2 dB for preshoot
0110b: 0 dB for deemphasis, 2.5 dB for preshoot
0111b: -6 dB for deemphasis, 3.5 dB for preshoot
1000b: -3.5 dB for deemphasis, 3.5 dB for preshoot
1001b: 0 dB for deemphasis, 3.5 dB for preshoot
Others: reserved

For 5GT/s Data Rate:
This bit sets the deemphasis level in Polling.Compliance state 

if the entry occurred due to the Enter Compliance bit being 

1b. Encodings:

0001b: -3.5 dB
0000b: -6 dB

For 2.5GT/s Data Rate:
The setting of this field has no effect. Components that 

support only 2.5 GT/s speed are permitted to hardwire this 

field to 0h.

Notes:
This bit is intended for debug, compliance testing purposes. 

System firmware and software is allowed to modify this bit 

only during debug or compliance testing.

11:11

RWS

0x0

compliance_sos:

When set to 1b, the LTSSM is required to send SKP Ordered 

Sets periodically in between the (modified) compliance 

patterns.

10:10

RWS

0x0

enter_modified_compliance:

When this bit is set to 1b, the device transmits Modified 

Compliance Pattern if the LTSSM enters Polling.Compliance 

substate.

9:7

RWS_V

0x0

transmit_margin:

This field controls the value of the nondeemphasized voltage 

level at the Transmitter pins.