Справочник Пользователя для Intel J1850 FH8065301455200
Модели
FH8065301455200
Datasheet
1077
PCU – Universal Asynchronous Receiver/Transmitter (UART)
21.2.1
FIFO Operation
21.2.1.1
FIFO Interrupt Mode Operation
Receiver Interrupt
When the Receive FIFO and receiver interrupts are enabled (FIFO Control Register, bit 0
= 1b and Interrupt Enable Register (IIR), bit 0 = 1b), receiver interrupts occur as
follows:
= 1b and Interrupt Enable Register (IIR), bit 0 = 1b), receiver interrupts occur as
follows:
•
The receive data available interrupt is invoked when the FIFO has reached its
programmed trigger level. The interrupt is cleared when the FIFO drops below the
programmed trigger level.
programmed trigger level. The interrupt is cleared when the FIFO drops below the
programmed trigger level.
•
The IIR receive data available indication also occurs when the FIFO trigger level is
reached, and like the interrupt, the bits are cleared when the FIFO drops below the
trigger level.
reached, and like the interrupt, the bits are cleared when the FIFO drops below the
trigger level.
•
The receiver line status interrupt (IIR = C6h), as before, has the highest priority.
The receiver data available interrupt (IIR = C4h) is lower. The line status interrupt
occurs only when the character at the top of the FIFO has errors.
The receiver data available interrupt (IIR = C4h) is lower. The line status interrupt
occurs only when the character at the top of the FIFO has errors.
•
The COM1_LSR.DR bit is set to 1b as soon as a character is transferred from the
shift register to the Receive FIFO. This bit is reset to 0b when the FIFO is empty.
shift register to the Receive FIFO. This bit is reset to 0b when the FIFO is empty.
Character Time Out Interrupt
When the receiver FIFO and receiver time out interrupt are enabled, a character time
out interrupt occurs when all of the following conditions exist:
out interrupt occurs when all of the following conditions exist:
•
At least one character is in the FIFO.
•
The last received character was longer than four continuous character times ago (if
2 stop bits are programmed the second one is included in this time delay).
2 stop bits are programmed the second one is included in this time delay).
•
The most recent processor read of the FIFO was longer than four continuous
character times ago.
character times ago.
•
The receiver FIFO trigger level is greater than one.
The maximum time between a received character and a timeout interrupt is 160 ms at
300 baud with a 12-bit receive character (that is, 1 start, 8 data, 1 parity, and 2 stop
bits).
300 baud with a 12-bit receive character (that is, 1 start, 8 data, 1 parity, and 2 stop
bits).
When a time out interrupt occurs, it is cleared and the timer is reset when the
processor reads one character from the receiver FIFO. If a time out interrupt has not
occurred, the time out timer is reset after a new character is received or after the
processor reads the receiver FIFO.
processor reads one character from the receiver FIFO. If a time out interrupt has not
occurred, the time out timer is reset after a new character is received or after the
processor reads the receiver FIFO.
Transmit Interrupt
When the transmitter FIFO and transmitter interrupt are enabled (FIFO Control
Register, bit 0 = 1b and Interrupt Enable Register, bit 0 = 1b), transmit interrupts occur
as follows:
Register, bit 0 = 1b and Interrupt Enable Register, bit 0 = 1b), transmit interrupts occur
as follows: