Справочник Пользователя для Intel J1850 FH8065301455200
Модели
FH8065301455200
Datasheet
5
13.8 SATA AHCI Memory Mapped IO Registers ........................................................... 179
13.9 SATA Primary Read Command IO Registers ........................................................ 218
13.10 SATA Primary Write Command IO Registers ........................................................ 223
13.11 SATA Primary Read Control IO Registers ............................................................ 225
13.12 SATA Primary Write Control IO Registers ............................................................ 226
13.13 SATA Secondary Read Command IO Registers..................................................... 227
13.14 SATA Secondary Write Command IO Registers .................................................... 232
13.15 SATA Secondary Read Control IO Registers......................................................... 234
13.16 SATA Secondary Write Control IO Registers ........................................................ 235
13.17 SATA Lane 0 Electrical Register Address Map ...................................................... 236
13.18 SATA Lane 0 Electrical Register Address Map ...................................................... 269
13.19 SATA Lane 1 Electrical Register Address Map ...................................................... 286
13.20 SATA Lane 1 Electrical Register Address Map ...................................................... 320
13.9 SATA Primary Read Command IO Registers ........................................................ 218
13.10 SATA Primary Write Command IO Registers ........................................................ 223
13.11 SATA Primary Read Control IO Registers ............................................................ 225
13.12 SATA Primary Write Control IO Registers ............................................................ 226
13.13 SATA Secondary Read Command IO Registers..................................................... 227
13.14 SATA Secondary Write Command IO Registers .................................................... 232
13.15 SATA Secondary Read Control IO Registers......................................................... 234
13.16 SATA Secondary Write Control IO Registers ........................................................ 235
13.17 SATA Lane 0 Electrical Register Address Map ...................................................... 236
13.18 SATA Lane 0 Electrical Register Address Map ...................................................... 269
13.19 SATA Lane 1 Electrical Register Address Map ...................................................... 286
13.20 SATA Lane 1 Electrical Register Address Map ...................................................... 320
USB Host Controller Interfaces (xHCI, EHCI)......................................................... 337
14.1 Signal Descriptions .......................................................................................... 337
14.2 USB 3.0 xHCI (Extensible Host Controller Interface)............................................. 339
14.3 USB 2.0 Enhanced Host Controller Interface (EHCI) ............................................. 340
14.4 References ..................................................................................................... 341
14.5 Register Map .................................................................................................. 342
14.6 USB xHCI PCI Configuration Registers ................................................................ 343
14.7 USB xHCI Memory Mapped I/O Registers............................................................ 380
14.1 Signal Descriptions .......................................................................................... 337
14.2 USB 3.0 xHCI (Extensible Host Controller Interface)............................................. 339
14.3 USB 2.0 Enhanced Host Controller Interface (EHCI) ............................................. 340
14.4 References ..................................................................................................... 341
14.5 Register Map .................................................................................................. 342
14.6 USB xHCI PCI Configuration Registers ................................................................ 343
14.7 USB xHCI Memory Mapped I/O Registers............................................................ 380
15.1 Signal Descriptions .......................................................................................... 539
15.2 Features ........................................................................................................ 540
15.3 References ..................................................................................................... 540
15.4 Register Map .................................................................................................. 541
15.5 HD Audio PCI Configuration Registers ................................................................ 542
15.6 HD Audio Memory Mapped I/O Registers ............................................................ 575
15.2 Features ........................................................................................................ 540
15.3 References ..................................................................................................... 540
15.4 Register Map .................................................................................................. 541
15.5 HD Audio PCI Configuration Registers ................................................................ 542
15.6 HD Audio Memory Mapped I/O Registers ............................................................ 575
®
PCI Express* 2.0 ................................................................................................... 699
17.1 Signal Descriptions .......................................................................................... 699
17.2 Features ........................................................................................................ 700
17.3 References ..................................................................................................... 703
17.4 Register Map .................................................................................................. 703
17.5 PCI Configuration Registers .............................................................................. 704
17.6 PCI Express* PCI Configuration Registers ........................................................... 705
17.7 PCI Express* Lane 0 Electrical Address Map ........................................................ 752
17.8 PCI Express* Lane 0 Electrical Address Map ........................................................ 784
17.9 PCI Express* Lane 1 Electrical Address Map ........................................................ 801
17.10 PCI Express* Lane 1 Electrical Address Map ........................................................ 832
17.11 PCI Express* Lane 2 Electrical Address Map ........................................................ 849
17.12 PCI Express* Lane 2 Electrical Address Map ........................................................ 880
17.13 PCI Express* Lane 3 Electrical Address Map ........................................................ 897
17.14 PCI Express* Lane 3 Electrical Address Map ........................................................ 928
17.1 Signal Descriptions .......................................................................................... 699
17.2 Features ........................................................................................................ 700
17.3 References ..................................................................................................... 703
17.4 Register Map .................................................................................................. 703
17.5 PCI Configuration Registers .............................................................................. 704
17.6 PCI Express* PCI Configuration Registers ........................................................... 705
17.7 PCI Express* Lane 0 Electrical Address Map ........................................................ 752
17.8 PCI Express* Lane 0 Electrical Address Map ........................................................ 784
17.9 PCI Express* Lane 1 Electrical Address Map ........................................................ 801
17.10 PCI Express* Lane 1 Electrical Address Map ........................................................ 832
17.11 PCI Express* Lane 2 Electrical Address Map ........................................................ 849
17.12 PCI Express* Lane 2 Electrical Address Map ........................................................ 880
17.13 PCI Express* Lane 3 Electrical Address Map ........................................................ 897
17.14 PCI Express* Lane 3 Electrical Address Map ........................................................ 928
Platform Controller Unit (PCU) Overview............................................................... 945
18.1 Features ........................................................................................................ 945
18.2 PCU iLB LPC Port 80h I/O Registers.................................................................... 948
18.1 Features ........................................................................................................ 945
18.2 PCU iLB LPC Port 80h I/O Registers.................................................................... 948