Справочник Пользователя для Intel J1750 FH8065301562600
Модели
FH8065301562600
Datasheet
1123
PCU – System Management Bus (SMBus)
Default: 00h
22.7.14
Notify Device Address Register (SMB_Mem_NDA)—Offset 14h
Access Method
Default: 00h
Type: Memory Mapped I/O Register
(Size: 8 bits)
SMB_Mem_SCMD: [MBARL] + 11h
MBARL Type: PCI Configuration Register (Size: 32 bits)
MBARL Reference: [B:0, D:31, F:3] + 10h
MBARL Reference: [B:0, D:31, F:3] + 10h
7
4
0
0
0
0
0
0
0
0
0
RSV1
SMBA
LT
DIS
HNW
A
K
EEN
HNINT
R
E
N
Bit
Range
Default &
Access
Description
7:3
00000b
RO
Reserved (RSV1): Reserved
2
0b
RW
SMBALTDIS: Software sets this bit to 1 to block the generation of the interrupt or
SMI# due to the SMB_ALERTB source. This bit is logically inverted and 'AND'ed with the
SMB_ALERTB bit of HSTS register. The resulting signal is distributed to the SMI# and/or
interrupt generation logic.
1
0b
RW
HNWAKEEN: Software sets this bit to 1 to enable the reception of a Host Notify
command as a wake event.
0
0b
RW
HNINTREN: Software sets this bit to 1 to enable the generation of interrupt or SMI
when HOST_NOTIFY_STS is 1. This enable does not affect the setting of the
HOST_NOTIFY_STS bit. When the interrupt is generated, either INTRB or SMI is
generated, depending on the value of the SMI_EN bit (D31, F3, Off40h, B1). If the
HOST_NOTIFY_STS bit is set when this bit is written to a 1, then the interrupt (or SMI)
will be generated. The interrupt (or SMI) is logically generated by AND'ing the STS and
INTREN bits.
Type: Memory Mapped I/O Register
(Size: 8 bits)
SMB_Mem_NDA: [MBARL] + 14h
MBARL Type: PCI Configuration Register (Size: 32 bits)
MBARL Reference: [B:0, D:31, F:3] + 10h
MBARL Reference: [B:0, D:31, F:3] + 10h
7
4
0
0
0
0
0
0
0
0
0
NDA
RSV
1
Bit
Range
Default &
Access
Description
7:1
0000000b
RO
NDA: DEVICE_ADDRESS - This field contains the 7-bit device address received during
the Host Notify protocol of the SMBus 2.0 specification. Software should only consider
this field valid when the HOST_NOTIFY_STS bit is set to 1.
0
0b
RO
Reserved (RSV1): Reserved