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VSEH

Single-ended high level for strobes

(VDD / 2) + 0.175

Note 3

V

1,2

Single-ended high level for Ck, CK

(VDD /2) + 0.175

Note 3

V

1,2

VSEL

Single-ended low level for strobes

Note 3

(VDD / 2) - 0.175

V

1,2

Single-ended low level for CK, CK

Note 3

(VDD / 2) - 0.175

V

1,2

1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac) 

of DQs.

2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced 

ac-high or ac-low level is used for a signal group, then the reduced level applies also here.

3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU 

need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 26.

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and 

strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the 

requirements in the table below. The differential input cross point voltage VIX is measured from the actual 

cross point of true and complement signals to the midlevel between of VDD and VSS