Справочник Пользователя для Hynix HMT42GR7BFR4A-PBT8
Rev. 1.0 / May. 2014
27
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied
between MRS and ZQCL commands.
between MRS and ZQCL commands.
Ta
CK,CK#
RESET#
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
MRS
1)
1)
MRS
MRS
CKE
DON’T CARE
READ
MRS
T = 500us
COMMAND
ODT
BA
RTT
MR3
MR1
MR0
READ
MR2
READ
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
ZQCL
VALID
VALID
VALID
VALID
Tmin = 200us
Tmin = 10ns
Tmin = 10ns
tCKSRX
Tmin = 10ns
tIS
tIS
tIS
tXPR
tMRD
tMRD
tMRD
tMOD
tZQinit
tDLLK
TIME BREAK