Справочник Пользователя для Hynix 1GB DDR2 CL5 HMP112S6EFR6C-Y5
Модели
HMP112S6EFR6C-Y5
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3 / Dec. 2009 1
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3 / Dec. 2009 1
200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 1Gb version E
This Hynix unbuffered Small Outline Dual In-Line Memory Module (DIMM) series consists of 1Gb version E DDR2
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb version E based
Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of indus-
try standard. It is suitable for easy interchange and addition.
FEATURES
* This product is in compliance with the directive pertaining of RoHS
ORDERING INFORMATION
Part Name
Density
Organization
# of
DRAMs
# of
ranks
Materials
HMP164S6EFR6C-C4/Y5/S5/S6
512MB
64Mx64
4
1
Halogen free
HMP112S6EFR6C-C4/Y5/S5/S6
1GB
128Mx64
8
2
Halogen free
HMP125S6EFR8C-C4/Y5/S5/S6
2GB
256Mx64
16
2
Halogen free
•
JEDEC standard Double Data Rate 2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
•
All inputs and outputs are compatible with SSTL_1.8
interface
•
Posted CAS
•
Programmable CAS Latency 3,4,5, and 6
•
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
•
Fully differential clock operations (CK & CK)
•
Programmable Burst Length 4 / 8 with both
sequential and interleave mode
•
Auto refresh and self refresh supported
•
8192 refresh cycles / 64ms
•
Serial presence detect with EEPROM
•
DDR2 SDRAM Package: 60 ball(x8), 84 ball(x16)
FBGA
•
67.60 x 30.00 mm form factor
•
RoHS compliant & Halogen-free