Справочник Пользователя для Intel E7-4870 v2 CM8063601272606

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

267

Datasheet Volume Two: Functional Description, February 2014

PCI Express Error Injection Capability.

Defines a vendor specific capability for WHEA error injection.

0:0

RW

0x1

abort_inbound_requests:

Setting this bit causes IIO to abort all inbound requests on the DMI port. This 

will be used during specific power state and reset transitions to prevent 

requests from PCH. This bit does not apply in PCI Express mode. 
Inbound posted requests will be dropped and inbound nonposted requests 

will be completed with Unsupported Request completion. Completions flowing 

inbound (from outbound requests) will not be dropped, but will be forwarded 

normally. This bit will not affect S-state auto-completion, if it is enabled. 

Note: Requires CPU reset sequence to be completed.

31:1

RO

0x0

reserved:

0:0

RW1C

0x0

received_cpu_reset_done_ack:

31:20

RO

0x250

0x280 (Device 0 Function 0)

nxtptr:

Next Capability Offset  
This field points to the next capability or 0 if there isn’t a 

next capability.

19:16

RO

0x1

capver:

Capability Version.
Set to 1h for this version of the PCI Express specification

15:0

RO

0xb

extcapid:

PCI Express Extended Capability ID  
Vendor Defined Capability