Техническая Спецификация для Microchip Technology 24LC32A-I/SN Memory IC 32 K 4 K x 8 24LC32A-I/SN
Модели
24LC32A-I/SN
2002-2012 Microchip Technology Inc.
DS21713M-page 3
24AA32A/24LC32A
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I):
T
A
= -40°C to +85°C, V
CC
= +1.7V to +5.5V
Automotive (E):
T
A
= -40°C to +125°C, V
CC
= +2.5V to +5.5V
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
1
F
CLK
Clock Frequency
—
—
—
400
100
100
kHz
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
2
T
HIGH
Clock High Time
600
4000
—
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
3
T
LOW
Clock Low Time
1300
4700
4700
—
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
4
T
R
SDA and SCL Rise Time
(Note 1)
(Note 1)
—
—
—
300
1000
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
5
T
F
SDA and SCL Fall Time
—
300
ns
6
T
HD
:
STA
Start Condition Hold Time
600
4000
—
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
7
T
SU
:
STA
Start Condition Setup Time
600
4700
—
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
8
T
HD
:
DAT
Data Input Hold Time
0
—
ns
9
T
SU
:
DAT
Data Input Setup Time
100
250
250
—
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
10
T
SU
:
STO
Stop Condition Setup Time
600
4000
—
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
11
T
SU
:
WP
WP Setup Time
600
4000
—
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
< 2.5V (24AA32A)
12
T
HD
:
WP
WP Hold Time
1300
4700
4700
—
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
< 2.5V (24AA32A)
13
T
AA
Output Valid from Clock
(Note 2)
(Note 2)
—
—
—
900
3500
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
14
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
must be free before a new
transmission can start
1300
4700
4700
—
—
—
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
15
T
OF
Output Fall Time from V
IH
Minimum to V
IL
Maximum
20+0.1C
B
—
250
250
250
ns
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V (24AA32A)
16
T
SP
Input Filter Spike Suppression
(SDA and SCL pins)
—
50
ns
17
T
WC
Write Cycle Time (byte or
page)
page)
—
5
ms
—
18
—
Endurance
1M
—
cycles Page mode, 25°C, V
CC
5.5V
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a
T
I
specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site at
www.microchip.com.
application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site at
www.microchip.com.