Техническая Спецификация для Microchip Technology IC MCU OTP 2KX PIC17C42A-16/P DIP-40 MCP PIC17C42A-16/P
Модели
PIC17C42A-16/P
1996 Microchip Technology Inc.
DS30412C-page 191
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-12: MEMORY INTERFACE READ TIMING (NOT SUPPORTED IN PIC17LC4X DEVICES)
TABLE 19-12: MEMORY INTERFACE READ REQUIREMENTS (NOT SUPPORTED IN PIC17LC4X
DEVICES)
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
150
TadV2alL
AD15:AD0 (address) valid to ALE
↓
(address setup time)
0.25Tcy - 10
—
—
ns
151
TalL2adI
ALE
↓
to address out invalid
(address hold time)
5*
—
—
ns
160
TadZ2oeL
AD15:AD0 hi-impedance to OE
↓
0*
—
—
ns
161
ToeH2adD
OE
↑
to AD15:AD0 driven
0.25Tcy - 15
—
—
ns
162
TadV2oeH
Data in valid before OE
↑
(data setup time)
35
—
—
ns
163
ToeH2adI
OE
↑
to data in invalid (data hold time)
0
—
—
ns
164
TalH
ALE pulse width
—
0.25T
CY
§
—
ns
165
ToeL
OE pulse width
0.5Tcy - 35 §
—
—
ns
166
TalH2alH
ALE
↑
to ALE
↑
(cycle time)
—
T
CY
§
—
ns
167
Tacc
Address access time
—
—
0.75T
CY
- 30
ns
168
Toe
Output enable access time
(OE low to Data Valid)
(OE low to Data Valid)
—
—
0.5T
CY
- 45
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25
°
C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
OSC1
ALE
OE
AD<15:0>
WR
Q1
Q2
Q3
Data in
Addr out
150
151
160
166
165
162
163
161
'1'
'1'
Q4
Q1
Q2
Addr out
164
168
167