Техническая Спецификация для Nxp Semiconductors LPC2194HBD64,151 ARM7 Microcontroller 16kB LQFP 64 LPC2194HBD64,151

LPC2194_4

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is 
safe to begin code execution. When power is applied to the chip, or some event caused 
the chip to exit Power-down mode, some time is required for the oscillator to produce a 
signal of sufficient amplitude to drive the clock logic. The amount of time depends on 
many factors, including the rate of V

DD

 ramp (in the case of power on), the type of crystal 

and its electrical characteristics (if a quartz crystal is used), as well as any other external 
circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing 
ambient conditions.

The LPC2194 include up to nine edge or level sensitive External Interrupt Inputs as 
selectable pin functions. When the pins are combined, external events can be processed 
as four independent interrupt signals. The External Interrupt Inputs can optionally be used 
to wake-up the processor from Power-down mode.

The Memory Mapping Control alters the mapping of the interrupt vectors that appear 
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip 
flash memory, or to the on-chip static RAM. This allows code running in different memory 
spaces to have control of the interrupts.

The LPC2194 support two reduced power modes: Idle mode and Power-down mode. In 
Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. 
Peripheral functions continue operation during Idle mode and may generate interrupts to 
cause the processor to resume execution. Idle mode eliminates power used by the 
processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. 
The processor state and registers, peripheral registers, and internal SRAM values are 
preserved throughout Power-down mode and the logic levels of chip output pins remain 
static. The Power-down mode can be terminated and normal operation resumed by either 
a Reset or certain specific interrupts that are able to function without clocks. Since all 
dynamic operation of the chip is suspended, Power-down mode reduces chip power 
consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if 
they are not needed in the application, resulting in additional power savings.

The VPB divider determines the relationship between the processor clock (CCLK) and the 
clock used by peripheral devices (PCLK). The VPB divider serves two purposes. The first 
is to provide peripherals with the desired PCLK via VPB bus so that they can operate at 
the speed chosen for the ARM processor. In order to achieve this, the VPB bus may be 
slowed down to 

1

⁄

2

 to 

1

⁄

4

 of the processor clock rate. Because the VPB bus must work 

properly at power-up (and its timing cannot be altered if it does not work since the VPB 
divider control registers reside on the VPB bus), the default condition at reset is for the 
VPB bus to run at 

1

⁄

4

 of the processor clock rate. The second purpose of the VPB divider 

is to allow power savings when an application does not require any peripherals to run at 
the full processor rate. Because the VPB divider is connected to the PLL output, the PLL 
remains active (if it was running) during Idle mode.