Техническая Спецификация для Infineon Technologies IC MCU 25 SAK-C167SR-LM HA+ MQFP-144 INF SAK-C167SR-LM HA+

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C167CR
C167SR
Functional Description
 
Data Sheet
26
V3.3, 2005-02
 
3
Functional Description
The architecture of the C167CR combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C167CR.
Note: All time specifications refer to a CPU clock of 33 MHz
(see definition in the AC Characteristics section).
Figure 4
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resources, the X-Peripherals (see 
C166-Core
CPU
Port 2
Interrupt Bus
XTAL
Osc / PLL
WDT
32
16
Interrupt Controller 16-Level
Priority
PEC
External Instr. / Data
GPT
T2
T3
T4
T5
T6
SSC
BRGen
(SPI)
ASC0
BRGen
(USART)
ADC
10-Bit
16
Channels
PWM
CCOM1
T0
T1
CCOM2
T7
T8
EBC
XBUS Control
External Bus
Control
Dual Port
IRAM
Internal
RAM
2 KByte
ProgMem
ROM
128/32
KByte
Data
Data
16
16
16
CAN
Rev 2.0B active
Instr. / Data
Port 0
XRAM
2 KByte
Port 6
8
8
Port 1
16
16
16
Port 5
Port 3
15
Port 7
8
Port 8
8
Port 4
16
On-Chip XBUS (16-Bit Demux)
Peripheral Data Bus
16