Техническая Спецификация для Texas Instruments DDC11XEVM-PDK - DDC11xEVM-PDK Evaluation Module DDC11XEVM-PDK DDC11XEVM-PDK
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DDC11XEVM-PDK
DDC11xEVM-PDK Kit Operation
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7.3.1
Main Window Controls
A number of controls are always visible, regardless of the tab selected in the main tab control.
The Quit button causes the program to exit and releases system resources. The Refresh All button
updates the state of all FPGA registers and pins to those states set in the FPGA control tab. The Take
Data button causes an acquisition cycle to occur and loads data into the program memory and will update
the graph with the data if the Use Graph check box is checked.
updates the state of all FPGA registers and pins to those states set in the FPGA control tab. The Take
Data button causes an acquisition cycle to occur and loads data into the program memory and will update
the graph with the data if the Use Graph check box is checked.
Data can be displayed in a number of formats, selected with the Formatting controls. The options are:
•
Codes: data are displayed in raw codes or counts
•
% Full Scale: data are displayed as a percentage of the full scale range
•
PPM of FS: data are displayed in units of parts per million (PPM) of the full scale range
•
pC Scaled to Vref: data are displayed in picocoulombs
The reference voltage can be set in the Vref text box control. The default value is 4.096V, which
corresponds to the reference voltage provided by the onboard voltage references on the DDC
daughtercards, but may be adjusted if a different reference voltage is used.
corresponds to the reference voltage provided by the onboard voltage references on the DDC
daughtercards, but may be adjusted if a different reference voltage is used.
7.3.2
Main Window Menus
The Main window has three menus: File, Data, and Graph. This section describes the functions of each
menu item.
menu item.
File
→
Quit
This option releases the USB port, closes all windows, and exits the software.
Data
→
Save Data from Memory
Collected data can be saved to a standard comma-separated value (CSV) formatted spreadsheet file. No
header data are written to the file; only raw data. The columns are written in this order: Channel Name,
Reading #, Reading [codes], Range [0-7], Vref [V], # of Bits [16 or 20].
header data are written to the file; only raw data. The columns are written in this order: Channel Name,
Reading #, Reading [codes], Range [0-7], Vref [V], # of Bits [16 or 20].
Once a reading is made, the data can be saved to a file using the Save Data from Memory menu item.
The data can then be analyzed further in Microsoft Excel
The data can then be analyzed further in Microsoft Excel
®
or a similar spreadsheet application that can
parse data in user-defined CSV format.
Graph
→
Plot Data on Graph
If data are loaded into memory but not plotted on the graph (because the Use Graph check box is not
checked), selecting this menu item plots that data on the graph.
checked), selecting this menu item plots that data on the graph.
7.3.3
FPGA Control Tab
The controls on this tab directly affect the operating mode of the DDC device being tested. This section
explains the various fields and buttons that reside on this tab.
explains the various fields and buttons that reside on this tab.
7.3.3.1
Registers Group Box
The fields in this box hold all the data that are used by the FPGA to generate the waveforms for the
device under test and retrieve data. The following list summarizes of all the fields and the respective
functions. Refer to the individual DDC device data sheets for further information on valid clock times and
pin functions.
device under test and retrieve data. The following list summarizes of all the fields and the respective
functions. Refer to the individual DDC device data sheets for further information on valid clock times and
pin functions.
•
CONV Low Int: This is the number of DDC System Clock Cycles for the CONV signal to remain low
during integration. The actual time is listed next to the text box.
during integration. The actual time is listed next to the text box.
•
CONV High Int: This is the number of DDC System Clock Cycles for the CONV signal to remain high
during integration. The actual time is listed next to the text box.
during integration. The actual time is listed next to the text box.
•
CONV CONFIG: The default value of this control is Free Run, and should be used in the data
acquisition process. The other options should not be used.
acquisition process. The other options should not be used.
•
CLK (High) (Low): This sets the high and low times of the DDC clock. The default value is 3 in both
fields, representing the number of clock cycles that CLK will be high and low.
fields, representing the number of clock cycles that CLK will be high and low.
•
DDC CLK CONFIG: Choose Running to enable the DDC clock or Low to disable the DDC clock.
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DDC11xEVM-PDK User's Guide
SLAU234A – October 2007 – Revised July 2010
Copyright © 2007–2010, Texas Instruments Incorporated