Справочник Пользователя для Texas Instruments CC2650DK
WCLK
BCLK
A
Dx
n-1
n-2
n-3
2
1
0
n-1
n-2
n-3
Channel 0 (left)
Channel 1 (right)
WCLK period = 1/F
S
2
1
0
n-1
LSB
LSB
MSB
MSB
WCLK
BCLK
ADx
MSB
MSB
LSB
LSB
Right channel
Left channel
WCLK period = 1/F
S
n-1
n-2
n-3
0
n-1
n-2
n-3
2
1
0
2
1
0
Serial Interface Formats
Figure 22-6. RJF Interface Format
22.6.4 DSP
DSP is a single-phase format, [I2S:AIFFMTCFG:DUAL_PHASE] = 0, where WCLK is high for one BCLK
period, followed by each audio channel back-to-back. Data is sampled on the falling edge of BCLK and
updated on the rising edge of BCLK; this is configured by setting [I2S: AIFFMTCFG:SMPL_EDGE] = 0.
period, followed by each audio channel back-to-back. Data is sampled on the falling edge of BCLK and
updated on the rising edge of BCLK; this is configured by setting [I2S: AIFFMTCFG:SMPL_EDGE] = 0.
There is an optional idle period at the end of the clock phase between the last data channel and the next
WCLK period; logical 0 will be output during this period. The number of BCLK cycles in the phase must be
equal to or higher than the word length, as specified in the [I2S: AIFFMTCFG: WORD_LEN] register,
times the number of specified channels (determined by the most significant 1 in all the [I2S:AIFWMASKx]
registers combined).
WCLK period; logical 0 will be output during this period. The number of BCLK cycles in the phase must be
equal to or higher than the word length, as specified in the [I2S: AIFFMTCFG: WORD_LEN] register,
times the number of specified channels (determined by the most significant 1 in all the [I2S:AIFWMASKx]
registers combined).
When sample words are back-to-back, LSB of the previous sample will be output in the DATA DELAY
cycle.
cycle.
DSP Interface Format (Showing First Two of Eight Possible Channels)
1416
Integrated Interchip Sound (I2S) Module
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated